Current downscaling of MOS devices goes together with modifications of the transistor device geometry, the implementation of new materials and the introduction of new device concepts. Planar devices have been replaced by FinFET structures and new designs such as Gate All Around FETs are being considered to tackle future scaling issues. In parallel, Si has successfully been replaced by strained SiGe (or strained Ge) in high mobility channels as well as for the implementation of Source/Drain (S/D) stressors. A further reduction in transistors' dimensions leads to a reduction in the S/D contact area and an increase in contact resistance, which limits device performance. New approaches are required to significantly reduce contact resistance. The right materials with controlled doping and the best process technology to match interfaces are key parameters to solve this challenge.
This triggered the research community to assess alternative dopants, like Ga for pMOS devices. Imec reported record-breaking values for S/D contact resistivity (<109 W cm2) on Ga implanted Si0.4Ge0.6 layers. However, the reported processing scheme requires an unwanted high thermal budget (laser anneal) and does not provide the necessary doping profile conformality on patterned wafers. No literature reports about epitaxial growth of highly Ga-doped SiGe or Ge by means of CVD. Indeed, major challenges need be overcome such as: 1) the extremely low Ga solubility in Si which in turn leads to a severe risk for Ga precipitation and agglomeration and 2) the unwanted but expected carbon incorporation, as commercially available Ga process gases contain CxHy groups which may dissociate and/or incorporate during growth. Developing selective epitaxial growth schemes of S/D materials with higher active doping concentrations than currently available will enable continuation of current transistor scaling.
Within the frame of this PhD, the candidate will generate the fundamental understandings enabling the implementation of low temperature growth of group-IV semiconductors using Chemical Vapor Deposition, with a special focus on Ga + B co-doped SiGe in view of future device applications. The main scientific goal of this project is to gain insight in the epitaxial growth schemes and to understand the electrical and structural material properties of Ga + B co-doped SiGe. It will be imperative to establish (and create insight in) the correlation between the epitaxial process conditions and the material quality by addressing the important aspects of defect formation e.g. vacancy formation, Ga precipitation / agglomeration and their impact on dopant activation. With respect to exploring the novel dopant gallium in addition to conventional boron doping, the experimental studies on material deposition will need to be complemented with theoretical calculations to understand the atomic material structure.
Required background: master in materials science or in physics
Type of work: 50% experimental work + data analysis, 20% modeling, 15 % literature, 15% dissemination
Supervisor: Wilfried Vandervorst
Daily advisor: Clement Porret, Roger Loo, Geoffrey Pourtois
The reference code for this position is 1812-01. Mention this reference code on your application form.