Investigating the impact of etch process damage for complex storage memory application

Leuven - PhD
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Meer dan twee weken geleden

A deep dive into the nano-scale etch processes shaping up tomorrow's high density storage memories

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Research description

There is always an ever-growing demand of fast and reliable technologies for application in data storage. High scalability, low-current, non-volatility, and adequate write endurance are some of the key aspects which need to be researched for further advancements in memory technologies. Currently SRAM (static random access memory) is a dominant contributor to data storage, but it has its drawbacks which include scalability issues arising from the use of multiple transistors, current leakage and high power consumption. Potential candidates to circumvent these issues include resistive- and magnetic-RAM. While ReRAM works by changing of resistance across a dielectric solid-state material, MRAM, on the other hand, works by changing of resistance across a magnetic material -insulator-magnetic magnetic material sandwich. For extracting enhanced performances from such systems, new novel materials have to be investigated from time to time. For example, phase change material systems like GeSbTe, solid-state electrolytes like GeSe and memory selectors like a-InGaZnO4 are of interest in the field of ReRAM. For MRAM, CoFeB/MgO/CoFeB systems, whose thicknesses vary in the order of few nanometers, are of great interest. Therefore, their patterning into storage elements becomes a pivotal factor during the device fabrication process. The subsequent impact of the patterning process on its electrical performance also becomes crucial. While patterning these materials into storage pillars, it is absolutely necessary to ensure that the etch induced damage to the sidewall, material composition and crystallography is minimal. These can eventually cause the devices to be either electrically shorted or perform poorly. In addition, the process needs to be scalable.

 

Multiple etch solutions – based on reactive ion etch (RIE) and physical ion beam etch (IBE) – need to be investigated to tackle the above mentioned patterning issues and deliver scaled and electrically functional array of storage structures. RIE, as the name suggests, involves chemical reaction of the different stack layers with the gas molecules introduced into the chamber followed by release of volatile products. Hence, the etch chemistry depends on the composition of the device layers and hence, is a selective process. This etch scheme has the potential to pattern devices having straight sidewalls, but chemical damage to the sidewalls is apprehended. IBE is a process wherein an accelerated inert gas ion bombards a surface and removes material based on the principal of momentum transfer in elastic collisions. It provides the flexibility of angular etch making redeposition removal from the sidewalls feasible. It is non-selective, thereby numerous materials can be patterned with this technique. However, physical damage to the sidewall can affect device performance. Pattern profile may not necessarily be straight, hence, scalability can be an issue. In short, both techniques have their pros and cons.

 

In the framework of a PhD research activity, both RIE and IBE processes need to be investigated to understand the scope of 'novel-material based' device patterning and its subsequent scalability. The etch-induced damage at the sidewall can be categorized as crystalline, interlayer- and interface-based. The first and foremost task of the student will be to carry out an extensive literature review on the process of IBE, RIE and provide an overview of the impacts so far on different material systems. The PHD candidate will then be required to engage in carrying out simulations based on a well-established model, such as Monte-Carlo based binary collision or molecular dynamics, to understand the two patterning systems. The goal is to understand etchant-stack interaction as complexity is introduced into the system through the addition of multiple metallic or insulating layers of different crystallographic textures and increasing adjacent pillars (storage density for scaling). The interplay of redeposition (in case of IBE)/surface polymerization (in case of RIE) with the process induced damage is another avenue to explore in order to estimate the damage zone and the active region in the storage device. Softwares such as Sentaurus Sprocess, Silvaco or Intellisuite can be used for carrying out the outlined investigation in a broad scale. A key aspect of this study will also be to validate the simulations using experimental techniques and report on their capability for creating advanced memories. The proof of concept can be in the form of high resolution physical characterization based on electron diffraction/microscopy or through electrical and magnetic measurements. In summary, the student needs to build a database encompassing the physics and chemistry behind the etch processes and provide an outlook on the type of etch which appear to be suitable for the different material systems being researched now for replacing the conventional storage memory. In order to corroborate his/her findings, it is crucial for the student to work in a team comprising process and device experts (processing, integration, physical characterization, modeling, reliability, etc.).​





Required background: Masters of Physics, Material Science, Simulation -oriented (and interest to further develop it)

Type of work: 10% literature, 70% simulation, 20% experimental

Supervisor: Stefan De Gendt, Frederic Lazzarino

Daily advisor: Shreya Kundu

The reference code for this position is 1812-18. Mention this reference code on your application form.

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