Ever since the invention of the integrated circuit, transistor density has doubled every two years, leading today to the availability of nanoscale CMOS technology with a minimum dimension of 16nm, and next generations with 10 or 7nm expected soon. Complex systems on chip (SoC) are realized, consisting of billions of transistors on a single die. This does come at a price for the analog systems that must be implemented in the same SoC, as the typical parameters that are important for an analog design (gain, linearity, noise, etc.) are increasingly difficult to achieve because of the lowered power supply and the ever-shrinking transistor dimensions. On the other hand, increasing requirements from complex application ask for always more bandwidth, more dynamic range, and higher accuracy, at lower power consumption.
Because of the never-ending increase in the consumer's need for higher data rates, fifth generation (5G) cellular systems are currently being standardized. These will offer a 1000X improvement w.r.t. 4G systems, by serving more users simultaneously, at data rates of several Gbps, while staying with the battery-determined limits of power consumption.
In this PhD, the topic of high-performance analog-to-digital converters (ADC) in this context will be dealt with. In recent years, several circuit-level and architectural innovations have been reported that been able to substantially lower the power consumption of ADCs typically used in wireless and other systems. To achieve the 5G targets, another major step will be needed, especially for high-speed ADCs. Sampling speeds of up to 10GS/s are needed, with an accuracy of 10 or more bits.
Moreover, there is a very wide range of other applications that also require GS/s ADC speeds, such a millimeter-wave imaging, radar, or optical communications. The successful implementation of such devices at low power in a modern CMOS technology is a must also in those areas. If possible, the results of the research carried out in this PhD will also be applied to those applications.
In this project, Imec is looking for a motivated and innovative PhD student that will take up this challenge. The high speed potential of modern nanoscale performance must be exploited to achieve these very high bandwidths, but this will not be possible without significant innovation in both ADC architectures and detailed building block implementation. Deep knowledge of both possibilities and the limitation of the technology's devices (transistors and passive), combined with the art of analog design and digital and mixed-mode calibration loops can advance the state of the art in this field.
Required background: electrical engineering, analog integrated circuit design
Type of work: 20% literature, 30% architecture study, 50% design and simulation
Supervisor: Piet Wambacq, Jan Craninckx
Daily advisor: Ewout Martens
The reference code for this position is 1812-60. Mention this reference code on your application form.