The world of communication continues to demand for higher data rates. For example, we see that in wireless communication the upcoming 5G standard will have data rates up to 10 Gbits per second, which is about one order of magnitude higher than the currently available 4G standard. When these data rates are feasible, then more data will be transferred, putting high demands on the infrastructure to prepare and process these data. The data traffic requirements in supercomputers, servers, data centers, base stations, ... will need networks based on optical fibres, each carrying data at a rate that will largely exceed 100 Gbit/s while the bit error rate requirements are several orders of magnitude more severe than in wireless communication.
For many years, the downscaling of CMOS made this technology the most widely used one for the implementation of the electronics of optical communication links. However, CMOS downscaling is slowing down and the intrinsic speed of CMOS transistors almost does not grow anymore due to the increased influence of capacitive and resistive parasitics in a MOS device. To further enable an increase of the data rates, more complicated modulations are considered, such as PAM4. This modulation is widely used these days, enabling a communication link with two bits per symbol instead of one, such as in the classical NRZ (non-return-to-zero) modulation. However, more bits per symbol lead to reduced signal-to-noise ratios, giving less margin to deal with effects such as unwanted reflections, inter-symbol interference, ...
To enable a further increase of data rates in communication infrastructure, a technology would be needed that enables the design of faster complex optical transceivers than what can be done with CMOS nowadays. It is known that high-mobility semiconducting materials such as indium phosphide (InP) offer a higher electron velocity than silicon, leading to a higher cutoff frequency. However, technology limitations do not allow for complex InP circuits with a high yield.
Imec has been working since several years on co-integration of compound semiconductors (such as GaAs, GaN) with CMOS on 300 mm wafers and is now extending this activity to co-integration of InP transistors with CMOS, with very high speed applications as a target.
This PhD. targets the design of optical transceivers for symbol rates (or baud rates) exceeding 100 Gbaud (Gsymbols per second) using InP transistors in the core of the circuits. Initially, a commercially available InP process will be used to design simple subcircuits of optical transceivers. The know-how obtained from design cycles in commercial InP technologies will be used to better specify the needs for development of the InP devices that will be co-integrated with CMOS. In a later phase, more complex circuits will be designed based on this co-integration scheme.
This PhD. requires experience in analog integrated circuit design and a broad interest in optical communication and device physics.
Required background: Electrical Engineering with analog IC design experience
Type of work: 10% literature, 20% architectural study, 60% IC design, 10% experimental measurements
Supervisor: Piet Wambacq
Daily advisor: Mark Ingels
The reference code for this position is 1812-58. Mention this reference code on your application form.