The CMOS scaling driven by Moore's law is facing several challenges arising from the increasing complexities and abilities of photolithography to pattern required feature sizes. It revealed that the two-year timeframe of Moore's law has been dropped and moved to a three-year cadence (tick-tock-tock) of optimizing technology and micro-architecture for the first time in sub-14nm technology nodes.
A large number of disruptive and immerging technologies including vertical gate-all-around (GAA) and complementary MOSFET have been investigated to maintain a continual scaling of CMOS technologies. The heterogeneous integration of multiple technologies on the same logic die, which are becoming more viable with the advances in 3D wafer-stacking and sequential 3D technologies, can open a new landscape for EDA tools and design methodologies.
To utilize the benefits given by these new technologies, potential architectural paradigms beyond conventional ASIC design methodologies have emerged the research community. This is the goal of the proposed project.
- Profiling and identifying interesting use cases of 3D integrations for high-performance/servers, mobile, and IoT applications.
- Re-thinking of the conventional design approach of microprocessor architecture for 3D integration.
- Designing and modeling the Power-Performance-Area-Cost (PPAC) impacts of such 3D solutions.
RTL design experiences with Verilog/VHDL, computer architectures, digital circuit designs, and experiences in using commercial logic synthesis and place-and-route (Cadence, Synopsys) will be a plus point.
Required background: Computer Engineering, Electronic Engineering
Type of work: 40% modeling, 40% circuit design, 20% literature
Supervisor: Marian Verhelst
Daily advisor: Trong Huynh Bao, Julien Ryckaert, Alessio Spessot
The reference code for this position is 1812-37. Mention this reference code on your application form.