Portable electronic devices and mobile systems have now become a key part of the information centric world we live in. This has resulted in a steadily growing reliance on creating and consuming data, which must be available when and where it is needed. However, technology scaling is compromising current memory technologies, such as SRAM, DRAM and Flash, as charge storage and sensing mechanisms have become less reliable. New memory technologies promise game-changing features whose impact can be felt broadly, from embedded computers and mobile devices to datacenters. Several alternative Non Volatile Memory (NVM) technologies are currently being investigated to eventually satisfy the need for continuously higher storage capacity and system performance, lower power consumption, smaller form factor, lower system costs and long data‐retention capability.
Among these memory technologies, Spin Transfer Torque MRAM (STT-MRAM) has gained a lot of attention due to its scalability, low power and relatively low access times. In addition to this, STT-MRAM is also compatible with the CMOS process. Despite all these advantages, STT-MRAM also faces several challenges. The write process is still relatively inefficient and long compared to SRAM. In addition to this, the high current through the MTJ imposes a severe stress for the memory cell and leads to a time dependent degradation of the MTJ. This usually limits the use of STT-MRAM for low level caches. Secondly, the read and write operations share the same access path (through the junction) and this can impair the reliability (read disturb).
To mitigate these issues, Spin Orbit Torque MRAM (SOT-MRAM[2,3]) has been recently proposed. SOT-MRAM uses a three terminal MTJ-based concept to isolate the read and the write path compared to the two terminal concept of STT-MRAM. As a result, in SOT-MRAM the read and the write path are perpendicular to each other which significantly improves the read stability. Moreover, the current passing through the MTJ is much lower and also the write access is also supposed to be much faster, as the write path can now be optimized independently.
The aim of the PhD is the Modelling and Design of SOT-MRAM for high speed memory applications. The major part of this will involve circuit design and analysis of SOT-MRAM for representative target platforms and application domains. Another important aspect of the PhD work will be to model the electrical characteristics and predict their behavior of the device, based on SOT-MRAM technology data developed by imec. To this end, a close interaction between process and device experts and within a team consisting of experts in various fields (processing, integration, physical characterization, modeling, reliability, etc.) will be crucial. Interested candidates should contact both daily advisors for more ample information.
 C. Chappert et al., Nature Material (2007);  M. Miron et al., Nature (2011);  M. Cubucku et al., APL (2014);  G. Prenat et. al., IEEE Trans. on Multi-Scale Computing Systems, Vol. 2, pp.49-60 (2016),  K. Garello et. al, VLSI2018 proceedings C8-2 (2018)
Required background: electronic engineering
Type of work: 55% circuit design, 35% device modeling and design, 10% literature
Supervisor: Francky Catthoor, Jan Van Houdt
Daily advisor: Kevin Garello, Trong Huynh Bao
The reference code for this position is 1812-39. Mention this reference code on your application form.