As a consequence of our increasing reliance on information nowadays, both for home and personal use along with business and professional needs, more and more data is being generated, processed, moved, stored, and retained in multiple copies for longer periods of time. Research has shown that the biggest performance bottleneck with popular smart-phone apps such as Facebook and Google Maps is, in fact, how fast they can read and write a device's data storage. This suggests that without solving the 'Memory Bottleneck', the benefits of new networks and processors will be limited. Aggressive technology scaling has also, placed limitations on current data storage technologies.
Thus, several new Non Volatile Memory (NVM) technologies and corresponding selector devices are currently being investigated to eventually satisfy the need for higher storage capacity, system performance, lower power consumption, smaller form factor, lower system costs and long data‐retention capability. Resistive RAM (RRAM), Phase Change RAM (PC-RAM) and Magneto-Resistive RAM (MRAM) are among the more mature NVM technologies. Spin Orbit Torque MRAM, Domain Wall Memory, Conductive Bridge RAM etc are some of the more recent NVMs with interesting characteristics. However, replacing the heavily optimized existing storage memory design architectures is easier said than done. Crossbar 3D architectures with NV memory elements have emerged as the primary challenger to existing storage technology. These highly dense crossbar 3D architectures of emerging NVMs need heavy technology optimizations and radically new bitcell designs. Each technology also comes with a set of inherent flaws, like write endurance limitation, or high access latency, etc.
Several concepts of non-volatile memories like ferro-electric, charge-storage, or resistive switching are being investigated at imec as potential candidates for both embedded and storage class domains. In this PhD thesis, the different technologies will first be compared and evaluated from a technology perspective for the targeted platforms and application domains. The major part of this would involve behavioural modelling of the Memory and associated Selector options, statistical data incorporation and bit-cell design. The PhD candidate will also assist in the design and analysis of the SCM array to enable the NVM memory architecture. Another important aspect of the PhD work will be to assist in the evaluation the NVMs at the system level and characterize them with respect to performance requirements, block level definition, workloads and other key features. In order to realize this, a close interaction between circuit and system experts will be required.
Required background: Electrical Engineering, Physics, Materials Science
Type of work: 40% circuit design, 30% behavior modelling, 10% system evaluation, 10% software, 10% literature
Supervisor: Wim Dehaene, ,
Daily advisor: Manu Perumkunnil, Andrea Fantini
The reference code for this position is 2020-026. Mention this reference code on your application form.