The impressive growth of semiconductor industry in the past few decades has been driven by the CMOS technology scaling. Miniaturizing the CMOS devices provides larger integration density, higher performance while lower the power consumption. However, as CMOS scales down to node N5 and beyond, gate length scaling becomes increasingly difficult if not impossible. Furthermore, the resistance of local interconnect in advanced nodes becomes the main bottleneck in extracting performance benefit from CMOS technology scaling. Achieving power, performance, and area gain from CMOS technology scaling as predicted by Moore's law thus requires innovation in technology, device architecture, circuit, and system design. 3D integration has been perceived as the promising candidate for extending Moore's law without scaling the critical device/interconnect dimensions.
In this work the candidate will interact with different imec groups working on technology development, material selection, TCAD simulation, and design to identify the challenges and opportunities of 3D integration. The primary objectives are to come up with standard cell architecture, floor-planning, and efficient interconnect architecture to support semiconductor scaling using 3D integration approach. The system/circuit architectures used in the work will drive the imec logic technology roadmap.
Required background: Electrical engineering with CMOS design background, experienced in computer architecture, python programming would help
Type of work: 20% literature, 40% modelling, 40% design
Supervisor: Francky Catthoor
Daily advisor: Shairfe Muhammad Salahuddin
The reference code for this position is 2020-050. Mention this reference code on your application form.