Circuit design in thin-film technology on flexible substrates is a fascinating, yet little-known research area. It allows for chips which are thin and flexible, such as an NFC chip that can be seamlessly integrated in paper and directly read out by a smartphone.
Despite numerous successful circuits demonstrated, the field of flexible electronics faces several challenges. The first one stems from the inability to use bulk silicon, and thus the standard CMOS process. As a fabrication-suitable option when working on flexible substrates, metal-oxide semiconductors, such as the one based on IGZO, are used. However, metal-oxide semiconductors are n-type only semiconductors, i.e. this is a unipolar technology. This requires a different topology for even the simplest concepts, like an inverter. The second issue rises due to limitations in critical dimensions, yielding rather long transistor channel lengths typically available in thin-film electronics, between 1.5µm and 5µm. This makes all circuits significantly slower than their CMOS equivalents. Finally, a rewritable non-volatile memory (NVM) accompanying IGZO transistor has not yet become a standard. Different NVM concepts, including ferroelectric and flash memory, have been explored but failed to demonstrate reliability needed for their use in more complex systems.
That is why at imec we develop a resistive random-access memory (RRAM) compatible with thin-film technology. The current work focuses on individual memory cells, while the aim of this internship is to extend the existing design towards an RRAM matrix. The intended matrix size is between 128bit and 1kbyte, to ensure compatibility with the thin-film NFC tags. To achieve this goal, specific read and write circuitry needs to be developed. Important criteria are robustness, speed, memory retention and power consumption of the matrix.
You will start from learning the ins and outs of our RRAM cell, resulting in a usable simulation environment for the circuit design. Then, you will find the right unipolar topology for reading and writing the cells with the highest robustness and speed possible. To verify your design, you will simulate with our custom TFT models. The final step is to lay out the design in a test chip, tape it out and, if time allows, do the final characterization.
To make this internship a success, your interest in electronic design is essential. We are looking for a circuit designer who is (partially) familiar with the circuit design steps of a CMOS integrated circuit, as this is the platform from which the design will start. Considering the technology is not yet set in stone, there will be some discussion with the technologists, so some background knowledge about semiconductor fabrication might come in handy.
Type of project: Internship, Combination of internship and thesis
Duration: minimum 6 months
Required degree: Master of Engineering Science
Required background: Electrotechnics/Electrical Engineering, Electromechanical engineering, Nanoscience & Nanotechnology
Supervising scientist(s): For further information or for application, please contact: Ana Lebanov (Ana.Lebanov@imec.be) and Florian De Roose (Florian.DeRoose@imec.be) and Kris Myny (Kris.Myny@imec.be)
Only for self-supporting students.