The thesis is intended to explore an architecture and hardware design for binary neural networks for resource constrained sensor platform. The design will target a heart rate monitoring application from wrist-worn photoplethysmography (PPG) signals.
Wrist-worn PPG signals provide a pervasive solution towards measuring physiological parameters, e.g. heart rate. Due to its form factor advantages, they have gained popularity over ECG sensing modalities. However, data collected through PPG sensors suffer from interference due to motion artifacts when used in ambulant environment. CNN, LSTM, are popular deep learning algorithms, providing a powerful medium to solve critical problems and has its advantages over traditional feature-based machine learning approaches. We use a binary CNN-LSTM based approach to estimate heart rate from wrist-worn PPG data, collected in ambulant environment during intense motion.
For real-time operations, a hardware design of the framework is required in conjunction with the sensor front end. This will require understanding the algorithm, the specific network operation and develop an optimized architecture and hardware design in terms of area-power-accuracy. This will require a thorough literature review of existing designs for binary accelerators and implementing one for the given application. The candidate is expected to perform verification of the designed hardware and explore possibilities for demonstrating real-time operations on a FPGA or ARM core. The candidate is expected to have preliminary knowledge of Python, Matlab, C and sufficient hardware design knowledge using Verilog/VHDL/System Verilog HDL.
Type of project: Internship
Duration: 6-9 months
Required degree: Master of Engineering Technology, Master of Science
Required background: Biomedical engineering, Electrotechnics/Electrical Engineering
Supervising scientist(s): For further information or for application, please contact: Dwaipayan Biswas (Dwaipayan.Biswas@imec.be)
Imec allowance will be provided.