Convergence between logic and Memory are crucial to extend the performance of advanced system.
In the context of advanced Storage Class Memory and Non Volatile Memory, this project aim at the exploration of the design of Memory periphery to boost the performance of data transmission between different part of the chip.
Type of work: Literature search 30%, Circuit design and simulation 30%, Data analyzing, report, and presentation 40%
Type of Project: Internship; Thesis; Combination of internship and thesis
Duration: 3-4 months
Master's degree: Master of Engineering Science; Master of Science; Master of Engineering Technology
Master program: Computer Science; Electrotechnics/Electrical Engineering; Nanoscience & Nanotechnology; Physics
Imec allowance will be provided