Detection of Cu contamination from TSV into Si substrate by C-t measurements

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Cu contamination in 3D silicon chips is a matter of life and death for charge carriers: you will hunt traces of transistor-killer Cu contamination in silicon chips for 3D integration, by measuring the lifetime-shortening effect on electron and holes in MOS capacitors.

Stacking silicon chips or integrated circuits, ICs, on top of each other, is one of the new emerging technologies for increasing the performance and the miniaturization of integrated circuits. Stacking of chips with the same technology allows for example more transistors per footprint area, as well as floors in buildings allow more people to live in the same street address.  Chips with different technologies and functions, for example memory and logic, are placed on top of each other to save space in mobile devices, where the miniaturization is an essential requirement. As for other silicon chip, these stacked chips must communicate with each other by electrical signals, sent through a suitable interconnect network.  

The fundamental interconnect element of 3D stacked ICs is the TSV, or Through-Silicon Via. The TSVs consist of a vertical cylindric conductor, usually copper (Cu), crossing the silicon substrate and enabling the electrical connection between the frontside and the backside metallizations of a thinned chip, as illustrated in Fig. 1(a).

The TSV conductor is insulated from the silicon substrate by a liner and a barrier. The liner is a dielectric layer, usually SiO2, deposited after etching the TSV hole in the silicon. It insulates electrically the TSV from the silicon substrate. The barrier, on the other hand, is generally made of a thin conductive material. It prevents the diffusion of copper atoms or ions in the silicon substrate. Fig. 1(b) shows details of the TSV conductor, the liner, the barrier and the silicon substrate.

Two planar dielectric layers, namely Pre-Metal Dielectric or PMD and backside or BS passivation, insulate the top and the backside metallization or RDL, respectively, from the Si substrate.


The complete electrical isolation of the TSV Cu conductor from the Si substrate is of vital importance for the functionality of the 3D stacked IC. Not only the SiO2 layer must be continuous and without any defect which could create a conductive path to the substrate: the barrier material must also be without any defect or pinhole to prevent copper ions to diffuse into the oxide and from there into the silicon substrate, as illustrated in Fig. 1(b).

Indeed, copper is a strong contaminating specie due to its capacity to create highly efficient recombination centers in the middle of silicon bandgap thus changing transistor electrical characteristics. 





​​Fig. 1 (a) Schematic representation of a TSV cross-section, showing the TSV conductor connecting the lower interconnect level at the frontside to the RDL at the backside of a thinned wafer. Dimensions are not to scale. (b) Mechanism of Cu contamination from a TSV with a defective barrier: Cu ions can migrate through a small pinhole into the SiO2 insulator and into the Si substrate, thus damaging transistors located in proximity of the TSV

A technique potentially able to detect the Cu ion contamination of the Si substrate is based on the capacitance vs. time characterization, or C-t, of Metal-Oxide-Semiconductor or MOS capacitors. This technique provides information about the degradation of the minority carrier lifetime in the substrate side of the MOS, due to the presence of recombination centers generated by the Cu ions diffused into the Si substrate.


The objective of this thesis is to evaluate experimentally the possibility of the C-t method to detect Cu ion contamination from a TSV by measuring the C-t characteristic of MOS capacitors located in the proximity of the TSV itself. The experimental work will be based on extraction of the minority carrier lifetime from C-t measurements on MOS structures surrounding a TSV damaged by electrical overstress. In this TSVs, the barrier is damaged, and the Cu contamination action will be enhanced by a temperature treatment which facilitates the Cu ion diffusion.

Content of the thesis:

  • 30% theoretical
  • 40% experimental (electrical measurements)
  • 30% data analysis and interpretation

Type of project: Thesis

Duration: 6 months

Required degree: Master of Science, Master of Engineering Technology, Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology, Physics

Supervising scientist(s): For further information or for application, please contact: Emmanuel Chery ( and Michele Stucchi (

Imec allowance will be provided for students studying at a non-Belgian university.

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