Fundamental and practical aspects of gate oxide breakdown in VLSI technologies beyond 7nm

Leuven - PhD
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Meer dan twee weken geleden

Modeling the degradation of complex high-k layers to the atomic level in order to come to a practical methodology for dielectric breakdown reliability assessment.

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Time-dependent dielectric breakdown is a reliability issue that has received a tremendous amount of attention in the past by many research groups. Also in imec, a solid expertise exists on the modeling and statistics of TDDB. In the past decade, the problem disappeared from the academic radar – especially in FEOL – as it was not considered to be the most stringent reliability issue. The focus shifted to BEOL where intermetal dielectric thickness and line spacing reduced to the point that TDDB became a considerable problem. Typical BEOL TDDB concerns relate to dielectric quality and line edge roughness inducing local field-enhanced breakdown.
In recent technologies, TDDB has, however, returned as a FEOL reliability concern. The gate stack in modern technologies is carefully tuned for optimal operation. Different metal gates are combined with a dielectric stack consisting of various high-k components. Dipole-inducing implants and defect annealing are used to optimize the work function while at the same time minimizing the impact of charge trapping causing bias-temperature instabilities (BTI). Although this meticulous optimization was beneficial for operation and some reliability issues, it also reduced the breakdown strength of the gate stack, bringing TDDB back as a reliability problem.

A PhD study on TDDB will focus on two main aspects:

  1. Physical modeling and fundamental atomistic understanding of degradation. Physical models from the past (H-related and charge-trapping related models) still have loose ends and need revisiting. In particular, the microscopic mechanisms involved in field-induced or charge flux-induced defect generation, charging and migration are still unclear. Recent advances in ab-initio and atomistic modeling using the increasingly available computing power, can generate new insights in this aspect, resulting in improved physical models for degradation and breakdown prediction methodologies in advanced dielectric stacks. Furthermore, unexplored interactions from for example the presence of dipole layers in a dielectric stack on TDDB can be assessed at the fundamental level.
  2. Practical measurement and analysis techniques need revisiting. Fast measurement techniques like ramped voltage tests indicate reduced breakdown field strength in advanced gate stack layers resulting in little reliability margin. These extrapolations are crude and rely on established interpretation of breakdown in simple oxide stacks. Modifications to the extrapolation and statistical treatment – preferentially based on fundamental insight – will yield more precise estimates of the TDDB. Important aspects in this context are (i) the interaction between TDDB and other reliability issues like BTI and hot carrier-induced degradation, (ii) the impact of different WF gate materials, (iii) the polarity-dependent asymmetry in degradation yielding different breakdown in n- and p-FETs, (iv) the time constants involved in degradation.


Type of work: 40% experimental, 40% simulation and modeling, 20% literature

Required background: engineering science, (semiconductor) physics

Supervisor: Guido Groeseneken

Daily advisor: Robin Degraeve

The reference code for this position is 1812-92. Mention this reference code on your application form.

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