Artificial intelligence is changing our world by increasingly influencing different aspects of life. Some of the most powerful machine learning algorithms, called deep learning algorithms or deep neural networks, require vast amounts of computations and memory during training. As a result, training a neural network is often not efficient, as it demands time, space and energy. This leads to the following question: Can we make training of deep learning models more efficient?
In this PhD we will tackle this question by examining ways to make existing training algorithms (i.e. back propagation with stochastic gradient descent) more hardware efficient. Specifically, we will explore how we can reduce the memory and computational complexity of training, while retaining good algorithmic accuracy. Furthermore, we will think outside the box and examine less conventional and novel training algorithms.
Our goal will be to make on-chip training efficient, even on the edge. This way, we can develop smart chips, which are flexible in their functionality and have the ability to fulfill a range of tasks on both mobile devices and in the cloud. To achieve these goals, we will leverage Imec's know-how in AI-accelerator design, novel memory and logic technology and algorithm development.
Required background: Computer science, AI/machine learning, hardware knowledge/interest
Type of work: 70% modeling, 20% hardware, 10% literature
Supervisor: Marian Verhelst
Daily advisor: Bram Verhoef
The reference code for this position is 2020-054. Mention this reference code on your application form.
Chinese nationals who wish to apply for the CSC scholarship, should use the following code when applying for this topic: CSC2020-21.