Neural probes are used to record neuronal activity inside the brain, and are believed to pave the way towards future neuroprosthetics and brain-computer interfaces. On recent probes, more than thousand electrodes are spread across the probe’s shank with a 20 micron pitch, picking up neuronal action potentials in its close vicinity. Through these action potentials (also known as ‘spikes’), neurons are able to communicate with each other. The process of clustering recorded spikes according to their underlying neuronal origins is referred to as ‘spike sorting’, which allows to identify the activation times of individual neurons. The latter is crucial for unraveling the structure and transient functioning of neuronal circuits and for the control of neuroprosthetics.
However, the ever increasing electrode count on probes and the high sampling rates has led to a data transmission bandwidth problem. To circumvent this problem, the future vision is to embed spike sorting algorithms on the probe itself. Indeed, on-probe spike sorting would require to only transfer spike times instead of raw signals, which leads to a drastic data rate reduction. Furthermore, it would even allow to bypass the transmission stage and enable real-time closed-loop neuronal applications such as, e.g., neural stimulation.
A low-complexity spike sorting algorithm was developed in-house and is a candidate for such an on-probe processing. However, energy and area bottlenecks on the hardware-side currently hamper such on-probe integration. The goal of this Ph.D. project is to design an energy- and area-efficient digital hardware architecture and platform on which this algorithm can be efficiently mapped, and co-optimize the hardware together with the algorithm. In this work, the PhD student will be responsible to design a power-efficient neural processor for energy-efficient spike sorting on very high-density neural probes. The candidate will collaborate with algorithm design experts who will be responsible for developing the actual spike sorting algorithm. The candidate in turn will investigate novel architecture and circuit-level designs to allow area- and energy-efficient HW implementations. The candidate will be expected to completely design the neural processor, tape it out and validate it in the lab.
Required background: electrical engineer with a strong affinity for digital circuit design and methodology. For this work, we are looking for a candidate with strong knowledge of digital custom IC design (RTL, synthesis, PNR).
Type of work: 70% digital circuit design, 10% system design, 20% measurements and validation
Supervisors: Francky Catthoor & Chris Van Hoof
Daily advisor: Nick Van Helleputte
The reference code for this PhD position is SE1804-01. Mention this reference code on your application form.