The demand for high-speed communications is increasing daily. In order to enable the next generation communication protocols(5G, 6G), circuits are getting more complex than ever and are composed today of several chips, each implemented in different technologies optimized for a particular function. Downscaling of CMOS technology has allowed the integration of high-speed transceivers on Silicon chips, but power amplifiers using III-V technologies, and high-performance switches fabricated on SOI substrates remain preferred choice for RF Front-End circuits. In order to develop cost and power efficient RF systems, co-integration of these different devices becomes critical.
While typical CMOS is today optimized for digital applications, the goal of this PhD is to engineer RF components for high performance communications systems through co-integration of logic with RF optimized device technologies. The candidate will therefore interact with both circuit design and technology integration teams.
In this PhD, different device architectures (e.g., MOS, HBT, HEMT) and technologies (e.g., GaN, GaAs, Si) will be considered. The performance tradeoffs when these devices are integrated on a common platform with logic devices will be assessed. In particular, parasitics, EM isolation and temperature will be studied. As novel material and device integration schemes are required for such a hetero-integrated technology, the study will assess impact of defects and guide ad hoc process developments. Based on the system and circuit requirements, new high speed components compatible with core CMOS technology would also be invented in the frame of this Ph.D. Furthermore, the advanced devices fabricated at imec will be measured, and techniques for accurate characterization of parasitics will be applied and developed. From the devices measurements, compact models will be developed and used to assess the circuit performance. Finally, basic RF circuits will be designed to benchmark the performance of the different technological solutions.
Required background: electrical engineering
Type of work: 10% literature, 70% device technology, 20% IC design
Supervisor: Bertrand Parvais
Daily advisor: Veeresh Deshpande
The reference code for this PhD position is STS1712-30. Mention this reference code on your application form.