Future high-performance computing and information systems implemented in sub 14-nm CMOS nodes are expected to require chip-level I/O bandwidths beyond 25Tbps, with an available power budget of less than 500fJ per communicated bit. Such brutal I/O requirements both in terms of density and power efficiency will drive the adoption of optical interconnects integrated at the chip level. However, while optical links intrinsically have better scalability potential as compared to Cu interconnects, a key challenge in unlocking these benefits remains in scaling the optical “ports” or electro-optic transceivers that form the interface between the electronic IC and the optical links. Scaling the bandwidth density and power consumption of these transceivers requires aggressive optimization and co-design efforts, combining the best-in-class optical devices (laser, modulators, photodetectors, waveguides, filters, ...) with advanced modulator/laser drivers, receive amplifiers and control logic in scaled FINFET technology (10nm and below), capable of running at data rates of 50Gb/s and higher.
In this thesis, the PhD candidate will explore novel high-speed (50Gb/s and higher) and low-power transceiver circuit concepts and architectures in FINFET technologies, interfacing with a variety of advanced silicon photonic devices. These include Si ring modulators, Si (photonic-crystal) Mach-Zehnder modulators, and GeSi electro-absorption modulators at the transmit side, as well as Ge p-i-n photodetectors and Ge avalanche photodetectors at the receive side. Appropriate attention will be given to the co-design aspect between the electronic and photonic devices and the intermediate 3-D elements (micro-bumps, TSVs) in a common design environment, in order to maximize the optical link performance within the voltage constraints of scaled CMOS logic. This effort will require the development (e.g. in VERILOG-A) of accurate device models (both electronic and photonic), which will be part of the PhD work. Fully functional prototype demonstrators will be built, using imec’s 3-D enabled Si Photonics platform combined with FINFET logic sourced from a commercial foundry.
Required background: electrical engineering, engineering physics
Type of work: 10% literature survey, 25% simulation, 20% design and layout, 40% measurements, 5% reporting
Supervisor: Johan Bauwelinck, UGent
Daily advisors: Michal Rakowski, Joris Van Campenhout
The reference code for this PhD position is STS1712-22. Mention this reference code on your application form.