PhD researcher on investigating ion beam-based patterning technology for STT-MRAM application

Leuven - PhD
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There is always an ever-growing demand of fast and reliable technologies for application in data storage. High scalability, low-current, non-volatility, and adequate write endurance are some of the key aspects which need to be researched for further advancements in memory technologies. Currently SRAM (static random access memory) is a dominant contributor to data storage, but it has its drawbacks which include scalability issues arising from the use of multiple transistors, current leakage and high power consumption. A potential candidate to circumvent these issues is STT-MRAM (spin transfer torque-based magnetic random access memory). Originating from the phenomenon of giant magnetoresistance (GMR), this technology has the capability to demonstrate low switching currents, high endurance and simplified architecture leading to higher scalability. The memory element, critical to the storage application, comprises metallic layers (CoFeB, Co and MgO) whose thicknesses are in the order of few nanometers. These layers need to be patterned into pillars in such a way that the etch-induced crystallographic/magnetic damages to the different layers are minimal, and don’t produce electrical shorting at the pillar sidewalls. Ideally the magnetic and electrical properties of the memory element should remain unperturbed by the patterning process. In addition, the patterning technique should be scalable.

Multiple etch solutions – based on reactive ion etch (RIE) and physical ion beam etch(IBE) – are being investigated to tackle the above mentioned patterning issues, thereby delivering scaled and electrically functional STT-MRAM pillars. RIE, as the name suggests, involves chemical reaction of the different stack layers with the gas molecules introduced into the chamber followed by release of volatile products. The process can therefore be selective at times depending on the stack composition and can also be less anisotropic.  IBE is a process wherein an accelerated inert gas ion bombards a surface and removes material based on the principal of momentum transfer in elastic collisions. Unlike RIE, IBE is a relatively non-selective and anisotropic process which also provides the flexibility to control the angle of the ion beam during the etch process. The combination of angular etch and ion beam energy is known to have a significant impact on the sidewall redeposition removal (a primary cause of electrical shorting), pillar profile (targeting vertical sidewalls for tighter pitches) as well as any intermixing, interface and crystallographic damage produced in the layers along the pillar sidewalls leading to poor electrical performance.

In the framework of a PhD research activity, IBE process needs to be investigated to understand its scope in fabricating functional STT-MRAM devices as the pattern/pillar size shrinks and pitches scale down to 200 nm and below. The first and foremost task of the student will be to carry out an extensive literature review on the process of ion beam etch and its applications. The PHD candidate will then be required to engage in carrying out simulations based on a well-established model, such as Monte-Carlo based binary collision. The goal is to understand the ion-stack atom interaction as complexity is introduced into the system through the addition of multiple metallic/insulating layers of different crystallographic orientation and thicknesses <1 nm into the stack. Ion-atom interaction induced scattering between adjacent pillars is another phenomenon which needs to be taken into consideration when STT-MRAM (pillar) arrays are being studied. The ion-atom interaction is dependent on ion type, ion energy, ion current density, ion beam angle and stack layer composition and these in turn dictate the extent of sidewall redeposition  and damage. The magnetic damage at the sidewall can be further looked into and categorized as crystalline, interlayer and interface-based. The interplay of redeposition and damage is another avenue to explore to hypothesize the damage zone formation in a STT-MRAM pillar. Softwares such as Sentaurus Sprocess and Silvaco can be used for carrying out the outlined investigation in a broad scale. A key aspect of this study is to validate the simulations using experimental techniques and report on the capability of this etch technique for advanced memories (i.e. STT-MRAM). The proof of concept can be in the form of high resolution physical characterization based on electron diffraction/microscopy or through electrical and magnetic measurements. In summary, the student needs to build a database encompassing the physics behind the IBE process. In order to corroborate his/her findings, it is crucial for the student to work in a team comprising process and device experts (processing, integration, physical characterization, modeling, reliability, etc.).

Required background: physics, material Science, TCAD-based simulation knowledge

Type of work: 10% literature, 60% simulation, 30% experimental

Supervisor: Stefan De Gendt

Daily advisor: Shreya Kundu

The reference code for this PhD position is STS1712-48. Mention this reference code on your application form.

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