Specification of process parameters in microelectronics is becoming tighter and tighter as we go to smaller and smaller nodes. There is a clear need to use more and better information with right measurement sampling strategy to achieve such challenging control.
Goal of this study is to get fundamental understanding of Edge Placement Error (EPE). Whereas scaling was mainly resolution-limited at previous nodes, edge placement error is the limiting factor now. In simulation, EPE equals the simulated contour minus the design target. During production EPE isn’t directly measurable, instead only the relative EPE (between two layers) can be measured, and this relative EPE measurement is critical to yield. There are a multitude of contributors to EPE, including the mask, exposure, post-expose bake and develop, etch, film deposition, etc. Hence, getting an insight into the process parameters which influence EPE during the various semiconductor process steps is key to better control. This will be done in a process flow by identifying – key parameters in semiconductor process tools that are influencing the final electrical yield . Combining metrology input, tool log files and electrical yield will provide large and different sets of data. Because of the size and variety of this set, a machine learning approach appears as the best candidate. But over-interpretation will need to be avoided, the treatment and analysis of the data will have to be strongly linked to the physical effects of process and metrology.
The candidate will need to get strong knowledge of various processes and their impact on the structures studied. He/she should get a good idea about physical behaviour of process and should have skills on modeling.
Imec provides wide range of advanced patterning capabilities as well as state of the art metrology capabilities. The candidate will identify the process platforms and metrology required to achieve the goal of the project.
Required background: electrical, material science, physics, some scripting experience (MatLab/Python)
Type of work: 40% wafer process , 40 % data analysis and modeling , 20 % literature study
Supervisor: Guido Groeseneken
Daily advisors: Sandip Halder, Philippe Leray
The reference code for this PhD position is STS1712-18. Mention this reference code on your application form.