Scaling has gone through difficult times where pitch scaling to reduce the footprint of the device has continued for many decades. However, scaling metal pitch is getting increasingly difficult as metal resistance increases substantially, and scaling of gate pitch has severe consequences on design of the device and source/drain.
In order to keep pace with the scaling trend without necessarily reducing critical feature dimensions it is mandatory to exploit the third dimension, hence staking multiple front-end layers and exploiting vertical transistors. However, although memory technology managed to exploit this evolution, a typical logic device is too random to directly make this evolution applicable as is. Therefore, the key for scaling is to scale functions instead of scaling gates and devices. Functional scaling revisits the general approach of using standard cell as primitive building blocks to build logic designs, attempting to build logic building blocks that are manufactured with a memory-like technology.
This Phd would focus on circuit and system designs from a functional scaling point of view. This may be by looking at various methods like stacking devices PMOS on top of NMOS etc. Exploration of various channel materials and device architectures would need to be considered. This may include 2D materials, vertical devices, lateral devices etc. A co-optimization of the circuit and device together with the technology will be key for making functional scaling possible.
Device architecture, layout, circuit design.
Type of work:
20% literature, 40% design, 40% simulation.
Supervisor: Marian Verhelst
Daily advisor: Julien Ryckaert and Praveen Raghavan
When you apply for this PhD project, mention the following reference code in the imec application form: ref. STS 1704-14.