As the technology advances, the integrated structures continue to evolve with decreasing dimensions and an increasing number of layers and complexity. The introduction of advanced materials on both chip and package level and the harsh environmental conditions during processing and operational use cause additional challenges for reliability analysis and prediction. In the microelectronics industry, the current materials selection is made with only a limited understanding of elastic properties, fracture properties and adhesion of thin continuous films deposited on a silicon substrate. However, these parameters do not sufficiently represent the failure behavior and structure stability of multilevel integrated structures, where each material exist as an individual part with different shapes and various cross-section geometries. On top of that, it is unclear whether the integrated materials maintain the same mechanical strength at smaller dimensions and confined structures. To answer this question and to gain more insight into root causes of failure processes, the semiconductor industry needs reliable, reproducible testing methods and strategies to monitor these parameters for fully integrated structures at nanoscale dimensions. To assess the mechanical strength at decreasing dimensions, high-resolution real time techniques are preferred over post mortem observations. The focus of this PhD first lies on the comparison of different experimental techniques (including in-situ nanoindentation based mechanical tests, high resolution electron microscopy and digital image correlation, among others). Secondly, these techniques will be used to study the impact of design and processing parameters on (a) the mechanical and fracture strength of complex multilayered integrated structures and (b) local adhesion at nanoscale and in confined dimensions in order to better understand the root causes of failure processes in multilevel integrated structures and to provide quantitative data that can be used to make reasonable predictions of chip/package interactions. Furthermore, the PhD student will work on: design of specific test structures (ex. nanoscale films, beams or pillars), different sample preparation techniques and scientific analysis of experimental results by comparing in-situ electron beam based nanoindentation mechanical tests, digital image correlation and finite element simulations. This PhD research supports different programs, including Interconnect, 3D, 3D NAND and/or Lithography.
Required background: materials science, physics
Type of work: 25% literature study, 25% technology study, 50% experimental work and scientific analysis
Supervisor: Ingrid De Wolf
Daily advisor: Kris Vanstreels
The reference code for this PhD position is STS1712-14. Mention this reference code on your application form.