In the era of IoT and wearables, ubiquitous healthcare monitoring is gaining a lot of interest. This requires ultra-low power complex systems. A suitable system consists of analog sensor interfaces to sense the various biomedical signals, local DSP to extract relevant medical information out of the raw recorded data, a wireless communication link to interface with the user or the cloud and a power management system to supply this all. Because of the power consumption of a wireless link, the need for local digital signal processing capabilities becomes ever more important. Fortunately thanks to scaling, we have seen a rapid rise in low-power digital compute and memory capabilities. However today’s solutions rely for a large part on general purpose DSPs and SRAM circuits and standard memory and processing architectures. While these offer great flexibility at an acceptable HW and power cost for most applications, existing circuits and architectures cannot reach the required power levels envisioned for true IoT and ubiquitous wearable healthcare platforms. Indeed the memory and DSP in existing biomedical platform typically consumes several 100s of uW, whereas analog front-end circuits consume typically an order of magnitude less power.
The proposed research is part of a more general effort to bring the power of the digital circuits at least an order of magnitude down to comparable levels as the analog. It is important to understand that these applications are far from high-performance digital computing. Datastreams are sampled a relatively low frequency (<1kSps for example) and the digital clocks speed is typically a few MHz to a few 10s of MHz. In current state of the art solutions, we see an emergence of fairly robust DSP compute capabilities in the form of impressive microcontrollers and reasonably sizeable memory arrays (128Kb-1Mb are no exception). However these are usually implemented according to industry standard methodologies which explains to a certain degree why the digital power consumption is high compared to the highly customized and application-optimized analog front-ends. Also significant portion of the digital power consumption is attributed to the memory circuits on the platform.
In this PhD, we will address this particular issue of memory energy consumption with the aim of achieving at least an order of magnitude lower power for, low-to-medium performance applications like IoT and wearable healthcare. This covers (a.o.) optimizing SRAM circuits, and develop new power efficient memory architectures for specific biomedical applications. However, the work will focus also on developing a design for these memories methodology that is compatible with existing industry standard tools to ensure that the outcome is transferrable to actual industrial applications in a later stage. Since in this specific application domain one of the biggest challenges will be leakage – because due to low-to-medium clock speeds involved dynamic power consumption is not expected to be the main problem – the PhD candidate will explore novel SRAM circuits and architectures in fully depleted SOI technologies which offer a number of interesting design options for dynamically scalable leakage performance. The candidate will be expected to validate the research experimentally in a proof-of-concept application demonstrator.
Required background: electrical engineer with a strong affinity for digital circuit design and methodology
Type of work: 60% circuit design, 20% system design, 20% measurements and validation
Supervisors: Chris Van Hoof, Wim Dehaene
Daily advisor: Mario Konijnenburg
The reference code for this PhD position is SE1712-14. Mention this reference code on your application form.