Over the past 15 years, substantial progress has been made in silicon-based photonic integration platforms. Using highly-confined Si waveguides, the footprint of photonic ICs has been dramatically reduced which has enabled e.g. CMOS compatible high-density electro-optic transceivers for short-reach optical interconnects. Contemporary Si photonic platforms use mostly group IV elements (Si and Ge) for the realization of active devices (modulators and photodetectors). However, there’s an increasing interest in monolithic integration of III-V materials for realizing superior active device functionality, including on-chip light emission, improved modulation and detection capability.
As a consequence of the significant evolution in the device technologies in recent years, and the achievement of stable device platforms, benchmarking the reliability of the photodetectors, waveguides, diodes and lasers becomes a live project to continue their development. The initial focus of this project is to examine the Silicon-based photonic devices under development in Imec, from a fundamental reliability perspective. This will involve quantify their initial properties, and assessing how these properties change as a function of stressing. This work will be extended to assess devices from the rapidly evolving III-V technologies as their integration progresses.
The impacts of defects at the hetero-interfaces involves simulation of the p(i)n junctions present in these devices (photodetectors, waveguides, lasers, diodes), and initially evaluating the impact of the group IV (Si/Ge) interface on device characteristics. As the next generation III-V / Silicon technologies continue to develop, these hetero-interfaces are becoming an exciting and new area of photonics research, and will become a significant point for the later part of the thesis. Attempts will be made to corroborate the simulation results will those measured from devices, in a bid to understand the key parameters that could impact the device characteristics (e.g. defects induced by the epitaxial processes employed in their fabrication).
This project will involve a significant amount of electrical characterization, analysis of measured data, and from that generation of models to explain the results, and extends to encompassing a prediction for the lifetime at operating conditions. In parallel the modelling of the devices will involve simulation efforts. This project does not involve working in the cleanroom per se, but will involve following the process flow of the relevant devices, in a bid to understand the processing challenges and their impact on the resultant device characteristics and indeed reliability.
Required background: physics, electrical engineering
Type of work: 10% dedicated to literature, 15% technology study, 50% experimental work, 20% simulation work, 5% reporting
Supervisor: Guido Groeseneken
Daily advisor: Barry O’Sullivan
The reference code for this PhD position is STS1712-20. Mention this reference code on your application form.