Research for low-power circuits has become important due to the increasing demand for battery-supplied systems needed for Internet of Things (IoT) applications. These systems, e.g. wireless networks and medical sensor applications, require a prolonged autonomy using only a limited amount of stored energy. Very low energy consumption has successfully been achieved by aggressively lowering the supply voltage in order to operate at the minimum energy point. This however occurs in sub-threshold operation which results in increased sensitivity to inter- and intra-die variations caused by the exponential relation between the threshold voltage V¬TH and the sub-threshold transistor current. On top of the already established time-zero variability, is the additional stochastic parametric shift of devices related to degradation mechanisms. This time-dependent variability leads to biasing and further widening of the time-zero performance distributions under circuit operating conditions. The exponentially decreased drive current combined with this variability leads to excessive timing margins to guarantee reliable operation. As a result, MHz-performance is hard to reach making sub-threshold circuits fall short of fulling the needs of modern ultra-low-power micro-architectures.
Excessive timing margins originate due to system-level ASIC simulation approaches such as Static Timing Analysis (STA). This allows designers to qualify their design across many conditions by abstracting all possible condition into a number of critical design corners, which aim to span the entire design space. Under the presence of variability and workload dependent reliability, these system-level simulation approaches, however, result in sub-optimal designs for ultra-low power in the sub threshold regime. This is due to standard CMOS logic families are not being optimized for sub-threshold operations (e.g. custom transmission gate logic is more robust than standard CMOS). Furthermore, their sensitivity to variability and reliability is difficult to assess using a corner based design approach which leads to either run-time failures or over-design.
In this PhD we aim to change the paradigm of circuit design and design automation to enable large power and performance gains needed for future ultra-low power design. It will involve studying novel devices, such as vertical nanowires, tunnel-fets and junction less devices, which could suit ultra-low power design. This will be combined with careful exploration of logic families such a static CMOS or transmission-gate logic. In order to reduce excessive timing overheads on-chip mitigation approaches will be incorporated. These may include architectures that stall or flush the pipeline for timing failures, general latch based design that use time borrowing, or self-healing resilient architectures with an error recovery mechanism. Finally, incorporating variability and workload dependent reliability into a gate level simulation framework allows the investigation of the impact at the system level. This last step is crucial to benefit from optimizations performed at the device and circuits level. For instance, by combining STA with specific circuit workload knowledge, error detecting flip-flops can be inserted only on crucial parts of in the entire design reducing their overall overhead. This novel methodology will be developed during the PhD.
You will work in a team of digital circuit designers and interact regularly with device engineers and researchers that address variability and reliability aspects.
Required background: electrical engineering with CMOS design background preferably in the context of data path design and microarchitectures. Experience using EDA tools e.g. synthesis, static timing analysis or place and route is a plus.
Type of work: 20% literature, 20% device technology, 30% circuit design, 30% design automation
Supervisors: Guido Groeseneken, Francky Catthoor, Wim Dehaene
Daily advisor: Pieter Weckx
The reference code for this PhD position is STS1712-27. Mention this reference code on your application form.