Scaling digital CMOS permitted the MOSFET to operate at very high speed, enabling high-data rates communication systems. The never-ending demand for increased data-rate in wireless and wireline communication systems can only be realized within a decent power budget if the transistors can operate at increasing frequencies. However, a reduction of the analog speed is observed with the recent introduction of FinFETs, due to the large level of parasitics. Therefore, specific transistors architectures designed for high frequency operation have to be introduced.
The purpose of this PhD thesis is to investigate the technological solutions for the realization of very high speed circuits. In particular, the work includes the design, simulation, fabrication, and characterization of high speed transistors that needs to be co-integrated with scaled digital CMOS. The devices that will be considered are not limited to Si. Furthermore, sequential 3D techniques are foreseen for the co-integration with logic CMOS, since it enables short device-to-device interconnection, which is needed in modern mixed-mode high speed circuits. However, this technology imposes some process restrictions, in particular in terms of thermal budget. A circuit-level assessment of the developed technology will also be performed.
Electrical engineering. Knowledge of semiconductor device physics as a prerequisite and knowledge or experience in device simulations, fabrication and characterization as a plus.
Type of work:
10% literature study, 65% device development (TCAD and processing), 10% measurements, 15% circuit level simulations.
Supervisor: Piet Wambacq and Nadine Collaert
Daily advisor: Bertrand Parvais
When you apply for this PhD project, mention the following reference code in the imec application form: ref. STS 1704-13.