For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips leading to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue.
Integrated circuits commonly include electrically conductive microelectronic structures, which are known as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. These patterns are typically formed by conventional “top-down” lithographic processes. When patterning extremely small features with extremely small pitches, several challenges present themselves, especially when the critical dimensions of the via openings are around 10 nm or less. One such challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances on the order of a quarter of the via pitch. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment is able to keep up. Furthermore, the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of the lithographic scanners. As a result, commonly two, three, or more different lithographic masks may be used, which tend to increase the costs. At some point, if pitches continue to decrease, it may not be possible, even with multiple masks, to print via openings for these extremely small pitches using EUV scanners. Therefore, novel bottom-up patterning techniques are getting more and more attention, such as self-aligned multiple patterning, directed self-assembly and fully self-aligned vias.
The research line proposed in this PhD proposal is functional to the fully self-aligned vias concept, where the growth of the desired dielectric material is confined to a pre-patterned area while inhibited on the remaining surface. On one hand, Atomic Layer Deposition (ALD) is a method to deposit thin films by a self-limited surface adsorption of gas-phase precursors and surface reactions between adsorbed precursors and reactants molecules, allowing a tight control of the deposited material thickness and quality at the atomic scale. On the other hand, the deposition of monomolecular organic films (such as self-assembled monolayers, SAMs) or functionalized polymeric layers is a simple and versatile method to control surface design and selectivity. The SAM or polymeric films act as ALD inhibition layers that can prevent deposition in certain surface areas, enabling area selective deposition (see figure). Two SAM deposition methods will be explored, i.e. from organic solvents (dip-coating and spin-coating) or from vapour phase (in a CVD-like reactor). The density and thermo-chemical stability of the organic inhibition layer is of paramount importance in order to withstand the ALD conditions, such as thermal budget, precursor type and dose, gas flow and pulse/purge duration. Two main mechanisms of selectivity loss might be attributed to unwanted interaction mechanisms between SAMs and ALD: i) channeling of the ALD precursors through the SAM molecular units (if not dense enough), ii) modification of the SAM terminal group exposed to the surface. On polymeric films, the loss of selectivity might be attributed to surface energy/polarity modification. On the other side, the ALD deposition on the target areas might be “poisoned” by unwanted organic residues. The advanced characterization of the nano-scale organic and inorganic films both on blanket areas and in confined dimensions will be part of the generated learning and will benefit of the extensive expertise already present in imec. Defect generation mechanism and quantification will be tackled. The final goals of this PhD project are i) to generate the scientific understanding needed to design area selective deposition approaches for patterning applications in nano-electronic device fabrication based on both SAM/polymeric films and ALD; ii) to transfer the learning from blanket surfaces to relevant nano-scale patterns taking into account pattern profile and transition regions between growth and no-growth areas.
In our research program on area selective deposition we leverage imec’s 300mm pilot line and advanced node technologies to gain access to materials and patterned structures with dimensions in the sub-10 nm regime in order to enable industrially relevant innovation.
Chemistry, materials, nanotechnology.
Type of work:
10% literature study, 90% experimental work.
Supervisor: Stefan De Gendt (Steven De Feyter)
Daily advisor: Silvia Armini
When you apply for this PhD project, mention the following reference code in the imec application form: ref. STS 1704-09.