Researcher SoC Architecture and Design Enablement for 3D

Leuven - Research & development
Meer dan twee weken geleden

Create the architectures and design flows for imec’s advanced 3D integration technology


Researcher SoC Architecture and Design Enablement for 3D

What you will do

You will help drive imec’s technology and architecture roadmap to build the 3D semiconductor technology of the near and far away future.

  • You will evaluate the impact 3D integration technology on SoC design.  You do so in order to guide future technology development as well as design enablement and EDA flows.
  • You will show the power and performance improvements that can be achieved using imec’s 3D interconnect technology, leveraging fine pitch 3D interconnect at place and routed SoC (subblock) level.
  • This fine pitch interconnect capabilities will require you to go well beyond the current capabilities of the tools and work together with EDA partners to create new design flows and get the tools ready for 3D stacked designs of the future.

What we do for you

  • We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow. 
  • We are proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through, 'our corporate university', we actively invest in your development to further your technical and personal growth. 
  • We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a competitive salary with many fringe benefits.

Who you are

  • The ideal candidate will have a PhD in Electronics, or a master with at least 3 years relevant industrial experience in physical implementation.
  • You have a background of digital implementation and SoC architecture for one or more application domains (Mobile, Server, …) and can make specification for different parts of SoC in different market spaces.
  • You have worked in multi-disciplinary teams, ideally both interacting with hardware designers as well as EDA vendors and foundry partners.
  • Prior experience designing wafer on wafer bonded systems or other 3D integrated integrated circuits is a strong plus.
  • Prior experience in EDA tool development is plus as well.
  • Experience with synthesis and physical implementation tool flows(Cadence Innovus or Synopsys ICC) is a must.

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