With significantly better performance than planar transistors, FinFET and its variants have become the mainstream of today's nano-scale CMOS technology. Continuous improvement of device performance has been contributed by dimensional scaling and implementation of novel device architectures (e.g. Gate-All-Around, Vertical or Stacked Devices). Accordingly, Gate-on-Fin features with ever higher aspect ratio is in high demand for Front-End-of-Line (FEOL) patterning. Profile control, as an important asset for plasma etching, has become more and more distinct at deeply scaled critical dimensions.
The main objective of this work is to explore the correction between Gate-on-Fin etching profile and plasma conditions. The Gate profile will be studied using X-SEM, CDSEM, and TEM. Plasma conditions including chemistries and source pulsing, will be screened and tuned for optimal Gate-on-Fin profiles.
The student will work in a 300mm cleanroom. Basic training on working regulations is mandatory as a starting. Technical training on plasma processing and relevant metrology will be arranged, so that the student can work independently. The result will be reported in our internal meeting (Etch-FEOL, Department of Advanced Patterning).
We are looking for a 6 months internship/thesis student at imec Leuven who shows good motivation and drives to understand the technology.
Type of project: Internship
Duration: 6 months
Required degree: Master of Engineering Technology or Master of Science or Master of Engineering Science
Required background: Chemistry/Chemical Engineering; Materials Engineering; Nanoscience & Nanotechnology; Physics
Supervising scientist: For further information or for application, please contact Liping Zhang (Liping.Zhang@imec.be).
Imec allowance will be provided.