Due to the device geometry scaling and newly introduced process options, latchup (LU) safe designs have become an increasingly challenging task of high-voltage (HV) or I/O circuit blocks in advanced bulk CMOS technologies. They are essential for system-on-chips found in mobile and wearable products. The bulk CMOS technologies have evolved over several process generations to provide cheaper products, smaller area, lower standby leakage, but more operating performance of computation speed and power . The dimension of a transistor and the spacing between different transistors are constantly shrinking in every new technology node. However, the reducing spacing between p-type and n-type transistors can significantly increase the risk of LU. Even more, next to sub-20nm, 3D fin structures have been used for maintaining the scaling down of the technology nodes. Not only the shrinking spacing but also the new introduced process options, such as STI depth and S/D epitaxy, can bring significant impacts on LU immunity in advanced CMOS technologies [2-5].
On top of the geometry scaling, the system-technology-co-optimization (STCO) has been proposed as a promising candidate for 5nm technology node and beyond [6-8]. More and more (sub-)system functions will be integrated in one chip with a special 3D vertically stacked or 2.5D interposer architecture. A system-level electrical reliability tests and electromagnetic compatibility or electromagnetic interference (EMC/EMI) become necessary to evaluate in the early stage of the technology/design/system development timeline. Transient induced latchup (TLU) [9, 10] in system-level and component-level electrical verifications will be a crucial reliability concern in STCO applications. Transient noise on power/ground buses of CMOS ICs has been reported as a risky trigger source to a latchup event . It can easily trigger on the LU event, even though TLU-sensitive CMOS ICs have already been verified by the quasi-static latchup test standard . Moreover, several prior works have shown the TLU events can be easily triggered by the system-level reliability electrical tests, such as the system-level ESD gun test, electrical fast transient test for EMC , and so on.
In this PhD program, the first task will focus on component-level LU and TLU immunity impacted by the process/layout/device/material options in advanced CMOS technology nodes. Based on an in-depth understanding of LU/TLU physical mechanism in these advanced technologies, the TLU exploration in the system-level reliability tests will be addressed in future STCO applications.
The candidate will join a well-rounded research team focused on developing the next generation of ESD and I/O solutions, within imec's renowned device reliability group.
Ref:  K. Domanski, IEEE IRPS, 2018.  C.-T. Dai, et al., IEEE IRPS. 2016.  C.-H. Huang, et al., EOS/ESD Symp., 2017.  C.-H. Huang, et al., EOS/ESD Symp., 2018.  J. Karp, et al., IEEE NSREC, 2017.  imec PTW materials,  J. Sun, IEDM invited talk, 2017.  R.-H. Kim, et al., SPIE, 2018.  M.-D. Ker, et al., IEDM, 2004.  M.-D. Ker and S.-F. Hsu, Transient-Induced Latchup in CMOS integrated Circuits, 2010.  JEDEC LU Standard.  IEC 61000-4 Standard.
Type of work: 10% literature, 25% technology study, 40% experimental work, 25% TCAD/System simulations
Required background: Master degree in Electrical Engineering (solid-sate or analog IC design field), Physics, or Material Science. Preferred: Si/Compound Semiconductor Device Physics, VLSI Process/Manufacturing/Integration, TCAD Process/Device Simulations, Layout/SPICE/EMC Design Environment.
Supervisor: Guido Groeseneken
Daily advisors: Shih-Hung Chen & Geert Hellings
The reference code for this position is 1812-91. Mention this reference code on your application form.