2022 International Interconnect Technology Conference (IITC)

This year at the 2022 International Interconnect Technology Conference (IITC), imec has a record number of 14 contributions, of which 10 papers and 4 posters, demonstrating its leading role in pushing the interconnect roadmap for the coming ten years. The papers show semi-damascene as a promising interconnect scheme for future logic nodes and highlight progress in middle-of-line metallization schemes, dual-damascene aspects, dielectrics and alternative metals exploration, and in reliability aspects. 

Imec highlights

5.3 Reliability Evaluation of Semi-damascene Ru/Air-Gap interconnect with Metal Pitch down to 18 nm (Alicja Lesniewska et al.)

Abstract—We evaluated the reliability of Semi-Damascene interconnects system fabricated by direct metal etch of Ru and Air-Gap as inter-metal dielectric. We show that intrinsically Ru does not drift into SiN and SiCO. Line-line TDDB results with Air-Gap widths of 8-16 nm (fixed line width of 10 nm) show a higher field acceleration factor compared to Dual-Damascene Ru/low-k systems and pass 10 years lifetime with Vmax > 0.75 V at 100oC for industry relevant line lengths. To address concerns related to moisture intake in Air-Gaps, we carried out humidity tests which showed no significant change in capacitance, leakage and VBD after 1000h at 85oC/85%RH. We also present that fully self-aligned vias pass electromigration and thermal storage tests.

8.3 Barrierless ALD Molybdenum for Buried Power Rail and Via-to-Buried Power Rail metallization (Anshul Gupta et al.)

Abstract— This work reports for the first time, a middle-of-line (MOL) compatible, barrier/liner-less ALD molybdenum (Mo) process on SiO2 used for Via-to-buried-power-rail (VBPR) and contact-to-active (M0A) dual damascene metallization. We also compare the MOL-compatible ALD process with the front-end-of- line (FEOL)-compatible ALD process used for BPR fill as reported in [1]. In addition, we report that Mo-BPR can withstand 800 °C anneal, demonstrating its compatibility with high thermal budgets of FEOL. Furthermore, we demonstrate for the first time, integrated (i.e. w/o air-break) precleans prior to Mo-VBPR deposition for contact formation with Mo-BPR. The precleans remove MoOx from Mo-BPR surface proven by SIMS characterization at blanket film level. The effectiveness of precleans is further proven at via level with a good agreement between measured and predicted Mo-VBPR resistance (R) landing on Mo-BPR. Finally, the first downstream electromigration tests on Mo-BPR annealed at 800 °C show no failures for >150 h at 5 MA/cm2 & 330 °C proving its robust behavior.

8.4 MP18-26 Ru Direct-Etch Integration Development with Leakage Improvement and Increased Aspect Ratio (Ankit Pokhrel et al.)

Abstract—Ru semi-damascene has been recently considered as a promising candidate to replace the conventional Cu dual damascene to meet the continued RC scaling needs in sub-2nm technology nodes. In this work, Ru lines with critical dimension of 9-10 nm and AR 3-6 targeting MP18-MP26 were fabricated in imec 300-mm pilot line using EUV-SADP technique and subsequent direct etch of Ru films for the first time. We demonstrate the optimizations made in patterning, metal etch, and clean that enabled the successful fabrication of Ru lines. Single line resistance of 10μm Ru with AR 3 shows that >90% of the devices meet the resistance target of <700 Ω/μm for MP20-26 and ~50% for MP18. Leakage current measurements between the core-defined and gap-defined Ru lines show >90% of devices meet the leakage target of 10-11A/mm.

10.3 Evaluation of BEOL scaling boosters for sub-2nm using enhanced-RO analysis (Anita Farokhnejad et al.)

Abstract—In this work, the impact of metal hybrid height (H^2) and airgap (AG) scaling boosters are evaluated based on an enhanced Ring Oscillator (RO) framework that accounts for Place and Route (PnR) aspects of the back end of line (BEOL) interconnects. When targeting best performance, extended AG with high aspect ratio (AR) lines appears to be the optimal choice as it allows reducing both capacitance (C) and resistance (R). Combining AG with H^2 provides minimum C at an increased R making it more suitable for power optimization.

11.5 ALD Mo for Advanced MOL Local Interconnects (Maryamsadat Hosseini et al.)

Abstract— This paper introduces ALD Mo as a potential replacement for W and Co as the conductor for logic MOL interconnects. 10nm ALD Mo without a liner and barrier has a very good adhesion on SiO2, SiN and SiCO dielectrics with resistivity as low as 19-22 μm.cm. We demonstrate for the 1st time a liner/barrier less ALD Mo fill capability in high aspect ratio trenches down to 10nm CD and show that ALD Mo does not drift into SiO2 and SiCO.

Overview imec papers

Wednesday, 29 June, 2022

Session 5: Reliability

• 5.2 Dynamics of electromigration voids in Cu interconnects: investigation using a physics-based model augmented by neural networks
  Ahmed S. Saleh et al.
• 5.3 Reliability Evaluation of Semi-damascene Ru/Air-Gap interconnect with Metal Pitch down to 18 nm
  Alicja Lesniewska et al.
• 5.4 Reliability benchmark of various via prefill metals
  Olalla Varela Pedreira et al.

Session 7: Unit Process and Integration

• 7.2 Enabling 3-level High Aspect Ratio Supervias for 3nm nodes and below
  Daniel Montero, et al.

Session 8: Advanced Interconnects

• 8.3 Barrierless ALD Molybdenum for Buried Power Rail and Via-to-Buried Power Rail metallization
  Anshul Gupta et al.
• 8.4 MP18-26 Ru Direct-Etch Integration Development with Leakage Improvement and Increased Aspect Ratio
  Ankit Pokhrel et al.

Poster session

• P1. A new methodology for modeling Air-Gap TDDB
  Yu Fang et al.
• P2. Stress and thermal stress evolution in Mo and Ru thin films
  Valeria Founta et al.
• P3. Improved Resistivity of NiAl Thin Films at Low Temperature for Advanced Interconnect Metallization
  Jean-Philippe Soulie et al.
• P5. Integration of Al2O3 Etch Stop Layer in 21nm Pitch Dual-Damascene BEOL interconnects
  Chen Wu et al.

Thursday, 30 June, 2022

Session 9: Advanced Interconnects

• 9.5 Low Resistance Cu Vias for 24nm Pitch and Beyond
  Marleen H. van der Veen et al.

Session 10: DTCO

• 10.3 Evaluation of BEOL scaling boosters for sub-2nm using enhanced-RO analysis
  Anita Farokhnejad et al.

Session 11: DTCO and Unit Process and Integration

• 11.2 Dual Damascene 28nm-Pitch Single Exposure EUV Design Rules Evaluation by Voltage Contrast Characterization
  Victor M. Carballo et al.
• 11.5 ALD Mo for Advanced MOL Local Interconnects
  Maryamsadat Hosseini et al.

Discover more