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CMOS: advanced and beyond

Imec enables next-generation computing, storage and interconnects – providing its partners with the disruptive breakthroughs they need to create their future products.

The high-performance compute market will continue to grow because of new application drivers. The 5G rollout will accelerate the already exponential growth of data. In combination with growing internet traffic and new datacenter applications such as supercomputing and high-performance computing-as-a-service, this increases the demand for high-end CPUs and GPUs inside (cloud) servers. Meanwhile, inside our smartphones, mobile SoCs need to integrate more functionalities in a form-factor-constrained IC.

To achieve that goal, imec collaborates with the entire IC value chain, forming one of the world’s largest R&D hubs for next-generation semiconductor research, building on advanced process steps and materials exploration, fundamental understanding and state-of-the-art fab infrastructure.

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Industry’s largest partner ecosystem for advanced CMOS and beyond

Imec has set up a unique environment for semiconductor research. A collaboration with the entire value chain, including the world’s major foundries, IDMs, fabless and fablite companies, material and tool suppliers, EDA companies and application developers.

It’s a collaboration where all the latest techniques and inventions can be brought together and co-optimized. An R&D hub with what’s arguably the world’s densest square mile of expertise, labs and fab infrastructure.

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Industry’s most advanced R&D 300mm cleanroom facility

Imec offers a neutral, open innovation R&D platform that involves suppliers deeply and at an early stage of process step and module development. Thanks to our close partnerships with leading tool and materials suppliers, we can do advanced process development and offer our partners the industry’s most advanced research infrastructure housed within a state-of-the-art 300mm cleanroom.

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Technology innovation from a system perspective

Emerging applications such as energy-efficient AI ICs in datacenters and edge devices require performance enhancements beyond those from traditional CMOS scaling. One way to achieve this is the simultaneous innovation of system architectures and technology requirements to allow for the most efficient combination of building blocks for the required functionality and performance – or system-technology co-optimization (STCO).

STCO starts by identifying the bottlenecks and challenges in existing systems. Those become the starting point for the exploration of new system architectures and technologies. The research loop is then closed by evaluating these innovations – and their cohesive integration – through prototypes or other hardware evaluation systems.

Because of its expertise across the technology stack – from semiconductor devices up to software – and its prototyping and manufacturing infrastructure and ecosystem, imec offers technology and system companies an STCO innovation sandbox for joint development of next-gen applications.

For imec, STCO is a guiding principle in a variety of research programs such as logic CMOS scaling and Advanced RF. STCO is also being explored at imec – USA Berkeley.

Check out this in-depth article on system-technology optimization.

Fast cycling between fundamental research, lab probing, and cleanroom enablement

Our scientists and engineers work closely with those of our partners. They’ve set up a fast R&D cycle, feeding the results of fundamental research to the fabs where materials and structures are probed and tested for suitability and characteristics.

From the fab, they flow to the cleanroom, looking for faultless manufacturability. The results, measurements and characterization are cycled back into the fundamental research.

Technology centers for advanced CMOS and beyond

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Expertise centers for advanced CMOS and beyond

Advanced patterning and key process steps
Patterning and process steps
Inline metrology
Metrology and characterization
Semiconductor reliability testing
Reliability testing and modeling

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