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Zsolt Tokei

Imec’s Zsolt Tökei discusses the latest outcome of imec's research on binary and ternary alloys for advanced interconnect metallization schemes with Silicon Semiconductor’s Phil Alsop.

Featured in the media

Resistivity research uncovers thin film star material

How imec is driving autonomous innovation

Jo De Boeck

Imec’s Jo De Boeck talks about the ITF World highlights in EE Journal’s Fish Fry podcast

Super Human Perception and New Compute Paradigms: How imec is Driving Autonomous Innovation

Jade Liu

New drug measurement and monitoring technology for accurate assessment of drug concentrations in blood, paves the way for personalized and faster care

Axithra, a spin-off of imec and Ghent University, raises 10M Euro

<a class="btn" href="/en/introduction-integrated-circuits">Follow our online course</a>

Looking for an introduction to microchips?

Julien Ryckaert

Imec highlights the potential of backside power delivery for high-performance computing and evaluates options for backside connectivity

Research update

Some major chip manufacturers recently announced the introduction of a backside power delivery network (BSPDN) in their logic roadmap.

In this article, imec, in collaboration with Arm, presents a design-technology co-optimization (DTCO) of one specific implementation of a BSPDN, where nTSVs and buried power rails are used for backside routing. They show how the potential of this BSPDN scheme can be fully harvested in a high-performance compute context.

In addition, they introduce alternative options for backside connectivity at the standard cell level, observing the largest scaling potential for a direct backside connectivity scheme.

Backside power delivery options: a DTCO study

Imec integrates thin-film pinned photodiode into SWIR sensors

Results published in Nature Electronics unlock the potential of thin-film sensors in infrared imaging

Imec integrates thin-film pinned photodiode into superior short-wave-infrared imaging sensors

Tom Aernouts

Molecular interface engineering: a&nbsp;pathway to scalable manufacturing

Metal halide perovskites show great promise for next-generation photovoltaic cells. However, commercialization requires industry-compatible processing techniques to address stability issues.

The largest efficiency losses and instability of perovskite solar cells are reported at the interfaces between the perovskite absorber and charge transport layers.

In this article, dr. Tom Aernouts presents an ammonium salt treatment to enhance two critical interfaces, creating highly efficient, stable, and scalable perovskite cells. 
&nbsp;

Enhancing efficiency and stability of Perovskite solar cells

Hasselt University and imec spin-off produces thin, flexible solar panels  

Pieter Van Nuffel

Enfoil, a new Hasselt University and imec spin-off, produces thin, flexible solar panels  

Monique Mols

Sarah de Crescenzo

Karen Lo

Skip Miller

Marcel Kemp

Peter Cheang

ASML is making a substantial commitment in imec's future state-of-the-art pilot line

Imec and ASML sign Memorandum of Understanding (MoU) to support semiconductor research and sustainable innovation in Europe

Scaling up GaN- and InP-based technologies for 5G and 6G

Nadine Collaert

GaN HEMTs and InP HBTs: integration on a Si platform and co-integration with CMOS components

Longread

With the advent of next generation 5G and 6G, telecom operators are pushing up the frequencies of the wireless signals.

While GaN high-electron mobility transistors (HEMTs) show promises for 28/39GHz operation, InP heterojunction bipolar transistors (HBTs) are expected to excel at 100GHz and beyond.

In this article, progress is reported in upscaling GaN HEMTs and InP HBTs to a silicon platform and in co-integrating them with CMOS components – requirements for next-gen high-capacity wireless communication.

Scaling up GaN- and InP-based technologies for 5G and 6G wireless communication

Listicle

Why are chiplets attracting the attention of the automotive industry?

From left to right:

Imec highlights critical process steps and modules for monolithic CFET devices

Vision

The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and pMOS devices within the same footprint.

In this interview, Hans Mertens, Steven Demuynck, and Anne Vandooren – three experts from the imec CFET team – explain how they gradually address this complexity.

They highlight CFET-specific process steps and modules and introduce backside connectivity as a key technology enabler to further reduce the size of standard cells.

Towards a process flow for monolithic CFET transistor architectures

Advanced semiconductor packaging enables compact, cost-efficient, high-performance 140 GHz radar & 6G mobile communications

Gerald Reischl

Low-loss, low-cost and mass-manufacturable PCB with embedded chip and waveguides paves the way for next-gen D-Band applications

Advanced semiconductor packaging approach from AT&S and imec lays the foundation for compact, cost-efficient, and high-performance 140 GHz radar & 6G mobile communications systems

Stories

Resistivity research uncovers thin film star material

How imec is driving autonomous innovation

Axithra, a spin-off of imec and Ghent University, raises 10M Euro

Looking for an introduction to microchips?

Backside power delivery options: a DTCO study

Imec integrates thin-film pinned photodiode into SWIR sensors

Enhancing efficiency and stability of Perovskite solar cells

Hasselt University and imec spin-off produces thin, flexible solar panels

Imec and ASML sign Memorandum of Understanding (MoU) to support semiconductor research and sustainable innovation in Europe

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