2026 Symposium on VLSI Technology and Circuits

Imec will be participating in 2026 Symposium on VLSI Technology and Circuits, which will feature selected presentations and panel sessions as well as advanced VLSI technology developments, innovative circuit designs, and the applications they enable, such as artificial intelligence, machine learning, IoT, wearable/implantable biomedical applications, big data, cloud / edge computing, virtual reality (VR) / augmented reality (AR), robotics, and autonomous vehicles. Join us to learn more on our latest breakthroughs and how to work with imec:  

PRESENTATION(S)

• SHORT COURSE
  • SCT2 | 3D Augmented Dimensional Scaling with Design-System Technology Co-Optimization
    SCT: Technology Short Course | Technologies Shaping the Future as Key Enablers for AI 
    Dwaipayan Biswas, Program Director XTCO Memory
• WORKSHOP
  • W1-1 | Cryogenic CMOS Devices - Performance, Variability and Defects
    W1 | Advances in Cryo-CMOS: Devices, Circuits and Applications 
    Alexander Gill, Principal Member of Technical Staff
  • W2-5 | DTCO for SRAM scaling and future opportunities using scaled emerging memories
    W2 | Embedded Memories in the Sub-2nm Era: SRAM Scaling Perspectives, Alternatives, and 3D Futures 
    Fernando Garcia Redondo, Principal Member of Technical Staff
  • W4-1 | A Scalable 300mm Platform for Developing Gate-Defined Silicon Spin Qubit Devices
    W4 | Design, System and Cross-Technology Co Optimization for Silicon Spin Qubits 
    Danny Wan, Program Manager Quantum Computing
  • W5-4 | AI and DRAM: Optimizing Memory for Machine Learning and Inference 
    W5 | High-Performance CMOS for DRAM: Enabling Mobile, Graphics, Datacenter, and HBM in the AI Era 
    Dwaipayan Biswas, Program Director XTCO Memory
  • W6-4 | Manufacturability of High-Density 3D Interconnects by Combining Early Si-Work, Machine Learning and Virtual Process Emulation
    W6 | VLSI Device Manufacturability: Improving Semiconductor Yield Through Virtualization 
    Zsolt Tokei, Fellow
• TECHNICAL SESSIONS
  • T1.3  First EUV-enabled integration route for 50 nm pitch N and PMOS transistors with 2D materials channel 
    from a 300 mm fab
    Session T1: T1 - Technology Highlights 
    Tom Schram¹, Quentin Smets¹, Goutham Arutchelvan², Chia-Hsien Yao³, Sui-An. Chou², Ming Yang Li², Dmitry Batuk¹, Teresa Rodrigues¹, Souvik Ghosh¹, Pawan Kumar¹, Benjamin Groven¹, Ann Opdebeeck¹, Daniel Montero Alvarez¹, Yuchao Jiang¹, Tanushree Sarkar¹, Kristof Kellens¹, Evi Vrancken¹, Catarina Rega Da Silva¹, Celia Mogultay¹, Tzu-hsien Shen¹, Vina Faramazi¹, Gouri Sankar Kar¹, Cesar Javier Lockhart de la Rosa¹, Mark Vandal², Anthony Yen³, Iuliana P. Radu², Etienne De Poortere^{3 
    1}imec, ²tsmc, ³ASML
  • T2.1 Improved Backside Contacting for CFET 
    Session T2: Backside Power Delivery 
    Cassie Sheng¹, Steven Demuynck¹, Dmitry Batuk¹, Jishnu Ganguly¹, Andy Peng¹, Thomas Chiarella¹, Pierre Eyben¹, David Schippers¹, Roger Loo¹, Subhobroto Choudhury¹, Thomas Dursap¹, Clement Porret¹, Lea Di Donato¹, Heath Huang¹, Serena Iacovo¹, Andrea Mingardi¹, Rami Khazaka², Conor Patrick Cullen², Daniel Casey², Farid Sebaai¹, Pallavi Puttarame Gowda¹, Rajendra Kumar Saroj¹, Anne Vandooren¹, Camila Toledo de Carvalho Cavalcante¹, Maryam Hosseini¹, Jerome Mitard¹, Kevin Vandersmissen¹, Nicolas Jourdan¹, Naveen Reddy¹, Il Gyo Koo¹, Efrain Altamirano Sanchez¹, Alfonso Sepulveda Marquez¹, Lucas Petersen Barbosa Lima¹, Naoto Horiguchi¹, Serge Biesemans^{1
    1}imec, ²ASM
  • T7.2  Dipole material-independent carrier mobility in dipole-first nMOS gate stack and introduction of multi Vt patterning-tolerant dipole-middle integration for NS/CFET
    Session T7: Gate Stack Processes 
    Hiroaki Arimura¹, Leo Lukose¹, Jimmy Stiers¹, Stephan Brus¹, Jacopo Franco¹, Ju-Geng Lai¹, Mohamed Ben Chroud¹, Camila Cavalcante¹, Thomas Chiarella¹, Inge Vaesen¹, Thierry Conard¹, Matias Bejide¹, Jerome Mitard¹, Min-Soo Kim¹, Steven Demuynck¹, Lucas Petersen Barbosa Lima¹, Serge Biesemans¹, Naoto Horiguchi^{1 
    1}imec 
  • C19.1  300-Channel Photometry Neural Probe with In-Pixel Adaptive-Noise ΔΣ Modulators Achieving 16.8 fA/√Hz Noise for High-Sensitivity Fluorescence Recording
    Session C19: Bio-Sensing and Molecular Interfaces
    Mengyu Li¹, Xiaolin Yang¹, Alejandro Lopez Rodriguez², Bastien Duckert¹, Pieter Neutens¹, Valentina Restrepo Jaramillo³, Phillippe Coppejans¹, Carolina Mora Lopez^{1 
    1}imec, ²EPFL, ³Universidad de Antioquia
  • C19.2 A Scalable, Unified Current-Mode ΔΣ Redox/pH Readout with Shared Potentiostat and Flicker-Noise Cancellation for High-Density Electrochemical Sensing
    Session C19: Bio-Sensing and Molecular Interfaces
    Joan Aymerich¹, Gerald Topalli², Jose Cisneros Fernandez¹, Javier Cuenca Michans³, Valentina Restrepo Jaramillo⁴, Chutham Sawigun¹, Carolina Mora Lopez^{1
    1}imec, ²Rice University, ³UAB, ⁴Universidad de Antioquia
  • C19.4 A 16-channel 97pArms 1MHz Bandwidth IC for Solid State Nanopore Sequencing
    Session C19: Bio-Sensing and Molecular Interfaces
    Qiuyang Lin¹, Wim Sijbers¹, Yixiong Hu¹, Eric Beamish¹, Wouter Botermans¹, Carolina Mora Lopez¹, Nick Van Helleputte^{1
    1}imec
  • TFS2.4 Backside Split-VDD Write-Assist Driven SRAM Macro Scaling in Nanosheet-Era
    Session TFS2: Advanced 3D Logic
    Ankit Singh¹, Dawit Abdi¹, Pieter Weckx¹, Aishwarya Singh¹, Arvind Sharma¹, Dwaipayan Biswas¹, Fernando Garcia-Redondo^{2 
    1}imec, ²imec UK
  • JFS3.1 5T+1 CFET SRAM with Dual-Bitline-per-Cell-Height Enabling Differential Readout and 12.5% Area Reduction
    Session JFS3: DTCO
    Dawit Burusie Abdi¹, Ankit Singh¹, Pieter Weckx¹, Arvind Sharma¹, Juergen Boemmels¹, Sheng Yang¹, Lynn Verschueren¹, Geert Hellings^{1 
    1}imec
  • JFS3.2 Scaling High Density Designs Towards Angstrom Nodes: BEOL Routability, Pin Accessibility Challenges and Impact of Gear Ratio
    Session JFS3: DTCO
    Ji-Yung Lin¹, Yu-Hua Yang², Halil Kükner¹, Shen Yang¹, Lynn Verschueren¹, Jürgen Bömmels¹, Francesco Dell’Atti¹, Odysseas Zografos¹, Anita Farokhnejad¹, Geert Hellings^{1
    1}imec, ²Novatek Microelectronics Corporation
  • T10.1 First Demonstration of Metal Interconnect At-Resolution Stitching with 0.55NA EUV Lithography for A10 Node and Beyond
    Session T10: Process Technology for CMOS Scaling
    Yannick Hermans¹, Yu Fang¹, Bart De Wachter¹, Vincent Wiaux¹, Tatiana Kovalevich¹, Stephane Lariviere¹, Andrea Mingardi¹, Ivan Ciofi¹, Victor Blanco¹, Sandip Halder^{1
    1}Angstrom Patterning Department (APD), imec
  • T10.3 High Yield Sub 20 nm Ru Direct Metal Etch Enabled by Single-Exposure 0.55NA EUV and dry MOR Technology
    Session T10: Process Technology for CMOS Scaling
    Alejandro Berdonces Layunta¹, Martin O'Toole^2,2, Etienne De Poortere², Tsann-Bim Chiou², Cyrus Tabery², Stefan Decoster¹, Victor M. Blanco Carballo¹, Bart De Wachter¹, Shubhankar Das¹, Elisabeth Camerotto³, Zhengtao Chen³, David Hellin³, Anuja De Silva³, Gosia Jurczak³ 
    1imec, ²TDC, ASML, ³LAM Research
  • T11.4 Interfacial engineering of scaled HZO in 3D-trench BEOL-compatible FeCAPs for high endurance (≥1013 cy.) and 2PR (>40 μC/cm2) at low (≥1.3 V) operating bias
    Session T11: FeRAM Array and Module
    Jasper Bizindavyi¹, Mihaela Ioana Popovici¹, Eyup Can Demir¹, Waleed Maqsood¹, Shruthi Subramanian¹, Gwon Kim^1,2, Alexandru Pavel¹, Nicolò Ronchi¹, Attilio Belmonte¹, Jan Van Houdt^{1,3 
    1}imec, ²Sungkyunkwan University, ³KU Leuven
  • C24.5 A dynamic supply temporal interference stimulation ASIC achieving 70% peak power saving and 21V compliance with accurate charge balancing
    Session C24: Circuits for Bio-Signal Acquisition and Neural Interfaces
    Haoming Xin¹, Roland van Wegberg¹, Stefano Stanzione¹, Vojkan Mihajlovic¹, Carolina Mora Lopez², Mario Konijnenburg¹, Nick Van Helleputte^{2 
    1}imec-Netherlands, ²imec
  • T15.4 Double-Flip Sequential CFET: Superior 3T Library Efficiency and PPA
    Session T15: Advanced Device Technology
    Sheng Yang¹, Jürgen Bömmels¹, Halil Kükner¹, Fabian M. Bufler¹, Lynn Verschueren¹, Hans Mertens¹, Anne Vandooren¹, Naoto Horiguchi¹, Anita Farokhnejad¹, Geert Hellings^{1
    1}imec
  • T17.4 High-Density Backside Connectivity with Remaining Bulk Silicon Substrate Using Self-Aligned Local Backside Dielectric Isolation for Frontside Active
    Session T17: Advanced Packaging and 3D Integration
    Takushi Shigetoshi^1,2, Peng Zhao², Liesbeth Witters², Violeta Georgieva², Daniel Montero Alvarez², Rajendra Kumar Saroj², Pallavi Puttarame Gowda², Thomas Altantzis², Tzu Hsien Shen², Nicolas Jourdan², Bart Kenens², Evi Vrancken², Jan Willem Maes³, Joeri De Vos², Gerald Beyer², Eric Beyne², Zsolt Tokei², Kan Shimizu¹, Yoshihisa Kagawa^{1 
    1}Sony Semiconductor Solutions Corporation, ²imec, ³ASM
  • T18.5 Vertically stacked Five-Word-Line IGZO FeFETs with Dual-Gate-Enabled Stable Erase Toward High Bandwidth Storage
    Session T18: Memories for AI Applications
    Zhuo Chen^1,2, Nicolò Ronchi¹, Roman Izmailov^1,2, Kruti Trivedi¹, Subhali Subhechha¹, Devin Verreck^1,2, Yang Xiang¹, Hongwei Tang^1,2, Geert Van den bosch¹, Attilio Belmonte¹, Maarten Rosmeulen^1,2, Valeri Afanasiev^1,2, Jan Van Houdt^{1,2 
    1}imec, ²KU Leuven

ORGANIZATION

• WORKSHOPS
  • W3 | Combining Light and Logic: Electronic–Photonic Co-Design for High-Performance Systems 
    Organizer: Ruud Oldenbeuving, Principal Member of Technical Staff
• SHORT COURSES
  • SCT: Technology Short Course | Technologies Shaping the Future as Key Enablers for AI Tapa 2 
    Organizer: Anabela Veloso, Principal Member of Technical Staff
• TECHNICAL SESSIONS
  • Session C1: High-Frequency Arrays for 6G and SATCOM 
    Co-Chair: Jorge Lagos, Principal Member of Technical Staff
  • Session T5: Technology Highlights 2 
    Co-Chair: Anabela Veloso, Principal Member of Technical Staff
  • Session C19: Bio-Sensing and Molecular Interfaces 
    Co-Chair: Carolina Mora Lopez, Scientific Director