2025 Symposium on VLSI Technology and Circuits

Imec

Imec will showcase 16 contributions at the 2025 Symposium on VLSI Technology and Circuits, including 15 first-authored papers. These papers highlight advancements in various areas such as radar sensing, high-speed memory, ultra-fast DACs, hybrid bonding for interconnects, nerve stimulation ASICs, power delivery in 2nm CMOS, wideband digital PLLs, CFET integration, high-power GaN devices, 3D organoid interfacing, selective deposition for interconnects, fine-tunable gate stacks, 3D DRAM processes, GAA technology for the A10 node, and SRAM scaling using CFET architecture.

Imec is also hosting a short course on heterogeneous system partitioning, led by senior fellow Eric Beyne, on June 9. 

Highlights

Imec highlights 2 VLSI papers on connected computing:

• The paper from Moeneclaey et al. announced a significant breakthrough in high-speed digital-to-analog conversion. The new 7-bit 150 GSa/s Digital-to-Analog Converter (DAC), fabricated in a 5nm FinFET CMOS process, achieves data rates of up to 300 Gb/s using PAM-4 modulation. Designed to address the growing demand for faster data center links, the DAC combines speed and power efficiency, setting a new standard for wireline data conversion.
  
  "A 7-bit 150-GSa/s DAC in 5nm FinFET CMOS”, B. Moeneclaey et al, presentation C12-1.
   
• The paper from Alian et al. showcases a new benchmark in RF transistor performance for mobile applications. They present a gallium nitride (GaN) MOSHEMT (metal-oxide-semiconductor high-electron-mobility transistor) on silicon (Si) that achieves both record efficiency and output power for an enhancement-mode (E-mode) device operating at low supply voltage. In parallel, the researchers demonstrated a record-low contact resistance of 0.024Ω· mm which is essential to further boost output power in future designs. The results mark a crucial step toward integrating GaN technology into next-gen mobile devices, particularly those targeting the 6G FR3 band between 7 and 24GHz.
  
  "High Power/PAE (27.8dBm/66%) Emode GaN-on-Si MOSHEMTs for 5V FR3 UE Applications", A. Alian et al, presentation T13-3. 
   

The following papers showcase imec’s progress in enabling the next steps in logic scaling and 3D system integration through innovations in interconnects, device architecture, and power delivery:

• In the first paper, imec presents a novel forksheet device architecture that allows to extend the nanosheet technology era to the logic A10 technology generation. In 2017, imec introduced the forksheet as a scalable device architecture to extend the gate-all-around (GAA) nanosheet-based logic roadmap in the least disruptive way possible. Concerns about manufacturability gave way to an improved forksheet architecture: the outer-wall forksheet. At VLSI 2025, imec shows through simulations the benefits of the outer-wall forksheet compared to the earlier inner-wall design: easier fabrication, superior gate control, connected n-p gates, and the ability to achieve full channel stress.  
  
  "Extending the Gate-All-Around (GAA) era to the A10 node: Outer Wall Forksheet Enabling Full Channel Strain and Superior Gate Control", L. Verschueren et al., presentation T22-1.
   
• Next, Imec highlights progress in wafer-to-wafer hybrid bonding, demonstrating the feasibility of scaling interconnect pitch to 250nm, an important milestone for enabling high-density tier stacking in 3D integration. The same study also introduced backside through-dielectric vias (TDVs) with 20nm via bottoms, showing how front-to-backside connectivity can be achieved after extreme wafer thinning, a key capability for future advanced packaging schemes.
  
  "High-Density Wafer Level Connectivity Using Frontside Hybrid Bonding at 250nm Pitch and Backside Through Dielectric Vias at 120nm Pitch After Extreme Wafer Thinning", L. Witters et al., presentation T6-1.
   
• A third paper highlights the benefits of backside power delivery networks (BSPDNs) in power-switched digital designs. While previous work focused on always-on domains, this study showed how BSPDNs improve IR drop and reduce core area in power-gated blocks, using a representative 2nm mobile processor design. The approach enables more efficient use of routing resources and fewer power switches, offering clear PPAC advantages for future mobile and low-power applications.
  
  "Backside Power Delivery for Power Switched Designs in 2nm CMOS: IR Drop and Block-level Power-Performance-Area Benefits", Y. Zhou et al., presentation T7-1.
   

This highlighted paper targets advances in integrated sensing and communication, especially for edge and IoT devices:

• At VLSI 2025 imec presents a new ultra-wideband (UWB) transceiver that combines communication and radar sensing in a single, compact chip. Fully compatible with the emerging 802.15.4ab standard, the design supports advanced features like presence detection, breathing monitoring, and angle-of-arrival estimation, while reducing antenna count and system complexity. The chip introduces a full-duplex architecture and signal conditioning techniques that improve radar performance without adding hardware overhead.
  
  "An IEEE802.15.4ab/a/z Compatible IR-UWB 2TRX with Dual-Antenna Full-Duplex 1x3 SIMO Radar Sensing and Aliasing Suppressing Semi-Synchronous TX", A. N. Bhat et al., presentation C2-2.
   

Imec showcases two highlight papers supporting next-generation medical and organ-on-chip technologies:

• One paper presents a flexible high-voltage stimulator ASIC for implantable peripheral nerve stimulation, introducing stimulus-synchronized charge balancing and on-chip common-mode regulation to support a wide range of current waveforms. The design, validated in saline, achieves robust performance in a compact, low-power form factor.
  
  "A Flexible HV Stimulator ASIC with Stimulus-Synchronized Charge Balancing and Embedded CM Regulation for Implantable Peripheral Nerve Stimulation", M. Zhou et al., C15-2.  
   
• Another contribution introduces an active perforated silicon microelectrode array (MEA) for seamless 3D organoid interfacing. Featuring integrated CMOS electronics for multimodal electrophysiology, the MEA supports high-resolution recording, stimulation, and impedance spectroscopy, offering a scalable platform for organ-on-chip research and disease modeling.
  
  "An Active Silicon Perforated MEA for Seamless 3D Organoid Interfacing with Low-Noise, Scalable Multimodal Electrophysiology", A. Rivero-Cortazar et al., presentation C24-1. 

Imec contributions overview

Monday, June 9th

Short course 1: Key VLSI Technologies in the AI Era

Anabela Veloso, Principal Member of Technical Staff at imec, will co-chair all sessions in this short course, from 8h25 AM to 4h35 PM. 
Eric Beyne, Senior Fellow at imec, will give a short course on "Heterogenous System Partitioning, the 2.5D and 3D Integration Landscape and Roadmap", from 10h25 AM to 11h25 AM. 

Tuesday, June 10th

Circuits Session 2: RF/mm-wave Tx and Rx

C2-2 | "An IEEE802.15.4ab/a/z Compatible IR-UWB 2TRX with Dual-Antenna Full-Duplex 1x3 SIMO Radar Sensing and Aliasing Suppressing Semi-Synchronous TX", A. N. Bhat et al. from 10h55 AM to 11h20 AM.

Technology Session 4: RRAm and MRAM

T4-3 | " High Density, High Speed STT-MRAM N7 Macros: Material and DTCO Exploration", D. Narducci et al. from 4h50 PM to 5h15 PM.

Evening Panel Discussion 2: Practical Circuits & Technology Training: Academia vs. Industry – Where Do We Learn the Most?

Carolina Mora Lopez, Scientific Director, will partake in the panel discussion on “Practical Circuits & Technology Training: Academia vs. Industry – Where Do We Learn the Most?”, from 8 PM to 9h30 PM.

Wednesday, June 11th

Circuits Session 12: Ultra High-speed Wireline

C12-1 | "A 7-bit 150-GSa/s DAC in 5nm FinFET CMOS”, B. Moeneclaey et al. from 10h30 AM to 10h55 AM.

Technology Session 6: Technology Highlights 2  

Anabela Veloso, Principal Member of Technical Staff at imec, will co-chair all presentations in this session, from 10h30 AM to 12h35 PM.  

T6-1 | "High-Density Wafer Level Connectivity Using Frontside Hybrid Bonding at 250nm Pitch and Backside Through Dielectric Vias at 120nm Pitch After Extreme Wafer Thinning", L. Witters et al. from 10h30 AM to 10h55 AM

Circuits Session 15: Biomedical Readout and Stimulation

C15-2 | "A Flexible HV Stimulator ASIC with Stimulus-Synchronized Charge Balancing and Embedded CM Regulation for Implantable Peripheral Nerve Stimulation", M. Zhou et al. from 2h25 PM to 2h50 PM.  

Technology Session 7: 3D Power Delivery Network

T7-1 | "Backside Power Delivery for Power Switched Designs in 2nm CMOS: IR Drop and Block-level Power-Performance-Area Benefits", Y. Zhou et al. from 2 PM to 2h25 PM. These results were created (in part) in the context of the NanoIC project.

Circuits Session 19: Frequency Generation

C19-4 | "A 2.3-15.8-GHz 8-Phase Injection-Ripple-Filtered Multi-Ring-Coupled DCO Enabling a Wideband Digital PLL", Z. Xu et al. from 5h40 PM to 6h05 PM.

Technology Session 10: Advanced CMOS Platform

T10-1 | "Monolithic CFET Flow Improvements Integrating Cover Spacer and Dual-WF RMG", C. Cavalcante et al. from 4 PM to 4h25 PM. These results were created (in part) in the context of the NanoIC project.

Thursday, June 12th

Technology Session 13: Power Devices

T13-3 | "High Power/PAE (27.8dBm/66%) Emode GaN-on-Si MOSHEMTs for 5V FR3 UE Applications", A. Alian et al. 9h20 AM to 9h45 AM.

Circuits Session 24: Circuit Techniques for Biomedical Applications  

C24-1 | "An Active Silicon Perforated MEA for Seamless 3D Organoid Interfacing with Low-Noise, Scalable Multimodal Electrophysiology", A. Rivero-Cortazar et al. from 10h30 AM to 10h55 AM.

Circuits Session 28: Sub-THz TRXs

Jorge Lagos Benites, Principal Member of Technical Staff at imec, will co-chair all presentations in the session about Sub-THz TRXs, from 2 PM to 3h40 PM.

Technology Session 17: Device Physics and Reliability

Anabela Veloso, Principal Member of Technical Staff at imec, will co-chair all presentations in this session, from 2 PM to 3h40 PM.  

Technology Session 18: Interconnects

T18-3 | "Selective Deposition and Ruthenium Superfill Exploration Beyond A10 Node Interconnects", M. van der Veen et al. from 2h50 PM to 3h15 PM.

Technology Session 19: Gate Stack and BEOL Transistor Processes

T19-3 | "Shifter materials and Stack Explorations for Vt Fine-Tunable Dual Dipole Multi-Vt Gate Stacks Compatible with Low Thermal Budget CFET", H. Arimura et al. from 2h50 PM to 3h15 PM. These results were created (in part) in the context of the NanoIC project.

Technology Session 20: DRAM

T20-1 | "Process Insights into 3D DRAM with Vertical Bit Line and Scalable GAA Transistor", N. Rassoul et al. from 4 PM to 4h25 PM. These results were created (in part) in the context of the NanoIC project.

Technology Session 22: DTCO and Design Enablement  

T22-1 | "Extending the Gate-All-Around (GAA) era to the A10 node: Outer Wall Forksheet Enabling Full Channel Strain and Superior Gate Control", L. Verschueren et al. from 4 PM to 4h25 PM. These results were created (in part) in the context of the NanoIC project.

T22-2 | "SRAM Scaling Opportunities Below 0.01 μm2 Using Double-Row CFET Architecture with Wordline-Folded Bitcell Design for Performance Optimization", D. B. Abdi et al. from 4h25 PM to 4h50 PM. These results were created (in part) in the context of the NanoIC project. 

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