ESSERC 2025

Imec

Keynote (September 9, 2025)

• Nadine Collaert, imec fellow, will deliver a keynote presentation titled 'Can GaN-on-Si Deliver the Wireless Future?' at 9:40 AM.

Workshops (September 8, 2025)

W1: Energy-Efficient Hardware Accelerators for Edge AI and Data-Intensive Applications

• Marian Verhelst, professor at the MICAS lab of KU Leuven and a research director at imec, will deliver a presentation titled "Efficient Design Flows for Decoupled Dataflow Accelerators". 

W6: Shaping the Future through Innovations in RF & Mm-Wave Design and Technology

• Chair: Björn Debaillie, program director.
• Abhitosh Vais, researcher, will deliver a presentation titled "III-V HBTs on Si substrate: A CMOS compatible technology for advanced communication systems".

W7: Tips and Tricks for a Successful Multi-Project-Wafer (MPW) Chip

• Romano Hoofman, strategic development director at IC-Link by imec and responsible for the innovation programs of the unit and for the coordination of the EUROPRACTICE Service, will deliver a presentation titled "Introduction to MPW Fabrication".
• Tobias Vanderhenst, leading industrial and academic tapeout operations at IC-Link at imec and Europractice, will deliver a presentation titled "Design Finishing and Sign Off".

Tutorials (September 8, 2025)

T1: Accelerators for Foundation Models and Event-Based Neural Sensing and Processing

• Wim Dehaene, full professor and head of the MICAS division of KU Leuven and principal scientist at imec, will deliver a presentation titled "In memory compute for ML, (when) does it make sense?" at 11:30

T3: From Design to Deployment: MEMS Sensors, Circuits and Their Integration Ecosystem

• Véronique Rochus, principal scientist, will deliver a presentation titled "Ultrasound Technology Evolution: From Piezo-Ceramic Devices to Optical and Flexible Sensors".

T4: High Performance Phase Locked Loops

• Chair: Nereo Markulic, principal member of technical staff.

Paper presentations

• Static and Statistical Modeling of LTPS TFTs for Robust Analog Design: Verified Through Amplifier and Comparator Measurements (Chen Wang, Xiaonan Xing, Seyed Mojtaba Sadati Faramarzi, Florian De Roose, Francois Berghmans, Qiuyang Lin, Chaohan W...)
• Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-Based Systems-in-Package Using Nanosheet Technology (Yukai Chen, Massimiliano Di Todaro, Bjorn Vermeersch, Herman Oprins, Daniele Jahier Pagliari, Julien Ryckaert, Dwaipa...)
• Stacked 2D Monolayer MoS2 Nanosheet FET with Gate-all-Around and Top Gates Architecture (Fengben Xi, Himanshu Sharma, Xiangyu Wu, Daire Cott, Robert K. Grubbs, Pawan Kumar, Tom Schram, Jean-Francois de Marn...)
• Exploring 2D TMD pFET Gate Stack Scalability Towards 1nm Electrical Thickness (Tien Dat Ngo, Zaoyang Lin, Chelsey Dorow, Xiangyu Wu, Robert K. Grubbs, Daire Cott, Kaustuv Banerjee, I. Hoflijk, Thi...)
• Performance improvement in sub-2nm node Nanosheet FETs through optimization of spacer interface and dopant activation by Andrea Pondini, PhD student, imec

NanoIC project

Visit our experts at the NanoIC dedicated booth to discover what the NanoIC project entails and offers. We are empowering start-ups, SMEs, and suppliers with access to training, cutting-edge chip infrastructure, and research opportunities for beyond-2nm technologies. More information will follow soon.

Event details

ESSERC 2025, the European Solid-State Electronics Research Conference, will be held in Munich, Germany, from September 8-11, 2025, featuring keynote presentations, industry sessions, focus sessions, tutorials, workshops, and awards.

The aim of ESSERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary.

Discover more