ESSERC 2024

Imec will be present at the 50th IEEE European Solid-State Electronics Research Conference (ESSERC) with 18 contributions, including 7 workshops, 1 tutorial and 10 first-authored papers. The contributions cover progress in advanced logic and memory devices and 2D materials, thermal insights for logic and 3D technologies, progress in power-efficiency of ADCs, scaling opportunities for photonic ICs, System-Technology Co-Optimization for AI/ML SoC design and finally progress in emerging devices such as nanopore-based sensors and wireless power transfer for neural implants.

To continue scaling of semiconductor technologies, close collaboration within the VLSI design research ecosystem and the collective use of Pathfinding- Process Design Kits are becoming a necessity. In light of this, imec is hosting a workshop, bringing in EDA companies Cadence, Synopsys and various universities for their view on building the proper infrastructure for this evolution.

Highlights

• Imec will be represented with a booth providing more info on its future NanoIC pilot line, its 2D experimental pilot line (2D-EPL), and imec.IC.link's ASIC development services. 
   
• The future of CMOS: building an infrastructure to fill the gap with the VLSI design research ecosystem 
  Imec is hosting a workshop to foster closer interaction within the design community and the academic research ecosystem, in view of the evolution of CMOS technologies. As an enablement to this interaction, imec will give a workshop on its N2 Pathfinding-Process Design Kit (P-PDK), explaining the importance of public PDKs for advanced nodes and how it can bridge the gap between industry and academia. Earlier this summer, imec hosted a first hands-on N2 P-PDK training.

Imec contributions

Monday, Sept 9, 2024

Tutorials

System Technology Co-optimization for 3D integrated AI/ML SOC design, Dwaipayan Biswas and Dragomir Milojevic

Workshops

2D Materials: Challenges and Opportunities 

• 2D-Experimental Pilot Line: Final project outcome, Inge Asselberghs
• Advances on 2D materials growth, Benjamin Groven

Emerging technologies in Advanced Computation, Advanced Functionalities, Ground-breaking Technologies: Impact on International Cooperation​

• New nanodevices architectures, Nadine Collaert
• Scaling semiconductor photonics - The trends and the challenges, Wim Bogaerts

Analog techniques for Neural Interfaces 

• Wireless Power Transfer for Implants, Stefano Stanzione

Pushing the power efficiency of data-converters and their limits 

• Massive Time-Interleaving for realizing compact extreme high-speed ADCs, Ewout Martens

The future of CMOS: building an infrastructure to fill the gap with the VLSI design research ecosystem 

• Pathfinding PDK, a window to the future technologies, Julien Ryckaert

Papers

Tuesday, Sept 10, 2024

Advanced Silicon Devices

• N2 Nanosheet Pathfinding-PDK (P-PDKTM) Including Back-Side PDN, A. Farokhnejad et al.
• Area-Efficient CFET Dual-Port SRAM with Backside Interconnect, D. Abdi et al

Wireless Rectifiers & Chargers

• A 170mV-to-1.8V Input Voltage Range DC-DC Boost Converter Using a 100nH Air-coil with Sub-µA Quiescent Current, W. Yu et al.

DTCO & System-Level Modeling

• Cold CMOS for Sustainable Datacenters, A. Beckers et al.

Wednesday, Sept 11, 2024

Reliabilty & Characterization  

• Thermal Insights into 3D Packaging of a High-Performance Server SoC in Advanced Nanosheet Technology, N. Kumar et al.
• Cryogenic Temperature Effects on 16nm FinFET Performance and Mismatch, E. Catapano et al.

Innovations in SAR ADCs

• A 4.2fJ/cs 2GSps 7.4B ENOB Loop-Unrolled SAR ADC for UWB Receivers, with Two Comparator Types and Wide Input Common-Mode Range, E. Bechthum

Biomedical Sensors 

• A 376µW per-channel, Drift-tolerant Translocation Recording Frontend with Event Detection for Nanopore Sensor Arrays, A. Das et al.

Thursday, Sept 12, 2024

Modeling of Emerging Devices 

• Detectability Limits of Single Proteins with Nanopore-Based Voltage and Ionic-Current Sensing, N. Akkan et al.

Advanced Memory Devices

• Understanding the Time Dependent Write and Read Performance of IGZO-Channel FeFETs, Z. Chen et al.
• A Novel DTCO-Driven 1T1R Bitcell for Sub-10ns STT-MRAM LLC Macros at N12 Node, F. García-Redondo et al.

Event details

The first “European Solid-State Electronics Research Conference - ESSERC” is scheduled for Bruges, Belgium, September 9-12, 2024.

The historical link with both ESSDERC and ESSCIRC remains and is also reflected in the new logo and the fact that the conference in Bruges will be referenced as the 50th ESSERC Conference. ESSERC has a single Technical Program Committee, a coordinating Steering Committee, a Conference Chair and Co-Chair and three Track Chairs, i.e., one for Circuits, one for Technologies and one for a Joint Track.

Discover more