/IEEE International Interconnect Technology Conference

IEEE International Interconnect Technology Conference

03 - 06 June 2024 | San Jose, USA

This June, imec will be present at the 2024 International Interconnect Technology Conference (IITC) with 18 contributions, including one invited paper on resolving nanoscale composition fluctuations and defects in advanced interconnects. The papers and posters that will be presented at IITC 2024 show progress on advanced interconnects, 3D packaging & integration, reliability, material exploration and novel processes.  The proposed innovations cover  multiple application domains, including high-performance computing, quantum technologies and superconducting digital logic.

 

Imec highlights

  • Resolving nanoscale composition fluctuations and defects in advanced interconnects: a crucial step to comprehend thin film resistivity (Invited), Claudia Fleischmann

With the introduction of new materials in the interconnect domain, we need to screen and control a broader range of material properties down to the (sub)nanometer length scale to realize low resistivity. This work will demonstrate how we can leverage Atom Probe Tomography and Positron Annihilation Spectroscopy for that purpose, as these methods allow to measure the spatially resolved composition and to identify point defects, respectively. The potential of each method will be highlighted by curated application examples, complemented with a brief introduction of each technique.

 

  • Two Metal Level Semi-Damascene Interconnects for Superconducting Digital Logic, Sara Iraci, et al.

In this paper we present a superconducting two-metal level (2ML) BEOL unit process based on NbxTi(1-x)N (NbTiN) that was developed in imec’s 300 mm pilot line using a semi-damascene flow and 193i lithography. The unit process features direct-metal-etch wires with minimum critical dimension (CD) of 50 nm and shallow planarized vias with minimum CD of 80 nm deposited at 420 °C, compatible with CMOS BEOL dielectrics. Normalized line resistance of 50 nm NbTiN wires show that 95% of the devices meet the expected resistance 800-1200 Ω/µm consistent with blanket films resistivity. Low temperature measurements show that NbTiN wires and vias have a critical temperature of 12-13.5 K and a critical current density of 80- 113mA/µm2.

 

  • Low Resistance Stacked Via Metallization for Future Interconnects, Marleen H. van der Veen et al.

We present stacked via and wire resistance predictions to find low resistive via metallization schemes that improve the system performance for sub-2 nm nodes. Implementing Ru vias with Cu wires at EUV patterned levels can give up to 60% resistance reduction. The circuit benefit of using Ru vias is determined with enhanced ring oscillator (RO) simulations. The Ru-Cu hybrid metallization in V2-M5 EUV printed layers gives a 10% frequency improvement as compared to stacks with semi damascene (SD) Ru and dual damascene (DD) Cu. The implementation of the selective Ru on Cu is demonstrated in metal pitch (MP) MP21-MP24 DD structures with yielding chains and vias that meet their resistance target.

 

  • Airgap Integration in MP18 Two-Level Semi-damascene Interconnects with Fully Selfaligned Vias, Gilles Delie et al.

Airgap integration in 18 to 26 nm metal pitch (MP) two-metal level semi-damascene interconnects with fully self-aligned vias (FSAV) on 300 mm wafers is reported. The first metal layer (Mx) is patterned using EUV-SADP with subsequent direct metal etch of the Ru film. Airgap is integrated at a targeted height of 4-6 nm below the top metal lines allowing for FSAV compatibility. 80% of kelvin vias landing on Mx at MP18 meet the <50ohm resistance target specification and 40% of them mee the via-to-line leakage target of <100 pA. The airgap line-to-line capacitance is found to be 40% lower compared to the dielectric gap fill reference.

 

  • Front-side Integration of Middle-of-line Stacked Contacts for Monolithic CFET, Victor Vega Gonzalez et al.

Complementary FET (CFET) is a device where n- and p-MOS transistors are stacked. In consequence, the source and drain metal contacts also need to be stacked. In this work, we investigate the high aspect-ratio (AR) patterning and metallization required for the formation of metal contacts in the monolithic CFET integration. The bottom contact is processed first by patterning deep trenches in between gates with AR > 13, CD = 17 nm and with a pitch of 60 nm. Subsequently, these high AR trenches are metalized, polished, and etched back. Afterwards, proper dielectric isolation needs to be in place before building the top contact. Finally, routing vias and the first BEOL layer are implemented all through the front side of the wafer for electrical tests.

 

Overview of imec contributions

 

Session 2: Advanced Interconnects I

  • 2.3 Airgap Integration in MP18 Two-Level Semi-damascene Interconnects with Fully Selfaligned Vias, Gilles Delie et al.

Session 3: Reliability & Failure Analysis

  • 3.5 Impact of ESD Events on TSV Liner Reliability, Emmanuel Chery et al.

Session 4: Metrology & Patterning

  • 4.1 Resolving nanoscale composition fluctuations and defects in advanced interconnects: a crucial step to comprehend thin film resistivity (Invited), Claudia Fleischmann

Session 7: Materials & Unit Process I

  • 7.3 Two Metal Level Semi-Damascene Interconnects for Superconducting Digital Logic, Sara Iraci, et al.

Session 8: Contacts to CMOS Devices & Novel/Emerging Technologies

  • 8.3 Front-side Integration of Middle-of-line Stacked Contacts for Monolithic CFET, Victor Vega Gonzalez et al.

Session 9: DTCO & Advanced Interconnects III

  • 9.3 Investigation of Graphene Cap Formation on NiAl by Low Temperature Thermal CVD (Student Paper), Yumehito Temmyo, et al. (co-authored by imec)

Poster Session

  • P1. Redefining 2-Level Semi-Damascene Interconnect Technology: Benchmarking three different Fully Self-aligned Via options, Giulio Marti et al.
  • P2. Self-aligned 8nm T2T as cell boundary in the middle-of-line, Philippe Marien et al.
  • P3. Demonstration of MP18-26nm Ru Semi-Damascene Spacer-is-Dielectric SADP Integration, Chen Wu et al.
  • P4. Technology benchmarking of copper electromigration using a grain-sensitive simulation framework (Student Paper), Ahmed S. Saleh et al.
  • P5. Patterning process and electrical yield optimization at the limits of single exposure EUV 0.33 NA: a pitch 26nm damascene process, Victor M. Blanco Carballo et al.
  • P6. Interconnect Delay Modeling of Critical Paths in Angstrom Nodes (Student Paper), Francesco Dell'Atti et al.
  • P15. Cyclic Etching of Mo Nanowire 17, Ivan Erofeev et al.
  • P16. Characterization of Siliconcarbonitride bonding layer for plasma activated direct fusion bonding, David Doppelbauer et al.
  • P17. Investigation of the enlargement of Ru grains and failure modes analysis in microsecond UV laser annealing, Zeinab Chehadi et al.
  • P23. Wafer-Level Electrochemical Deposition and Processing of Nanotwinned Cu RDL, Chih-Hao Hsia et al.

Session 11: 3D Packaging & Integration

  • 11.5 Bonding induced distortion in wafer-to-wafer bonding applications: how the scanner and Yieldstar can enable 3D integration, Victor M. Blanco Carballo et al.

Session 12: Materials & Unit Process III

  • 12.1 Low Resistance Stacked Via Metallization for Future Interconnects, Marleen H. van der Veen et al.

 

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