Imec
Imec is attending the 28th edition of IEEE IITC, held for the first time in Korea, with 17 presentations of which 14 first-authored and 2 invited. The presentations cover a wide spectrum of interconnect innovations, including advanced metallization schemes, electrical and reliability modeling, and new integration approaches for sub-2nm nodes. Topics range from semi-damascene process optimizations and via resistance to hybrid bonding, backside connectivity, and electromigration-aware design strategies. Giulio Marti, R&D engineer, and Blake Hodges, Superconducting Design Engineer at imec, are invited speakers. Furthermore, Zsolt Tokei, Fellow & Program Director Nano-Interconnects at imec, and Christopher Wilson, Equipment and Material Supplier Portfolio Director at imec, will (co-)chair a session at the conference.
Highlights
Imec will present 16nm pitch Ru lines in semi-damascene with record-low resistance. The Ru lines had an average resistance as low as 656W/µm. The 16nm pitch metal lines were fabricated using a semi-damascene integration flow optimized for cost-effective manufacturability, making it an attractive approach for fabricating the first local interconnect metal layer of the A7 and beyond technology nodes.
Read the full press release here.
Imec contributions overview
Tuesday, June 2nd
Zsolt Tokei, Fellow & Program Director Nano-Interconnects at imec, will co-chair all presentations in session 2 - Advanced Interconnects I (9h50 AM to 12PM)
Session 2: Advanced Interconnects I
- "Advancing pillar-based FSAV integration of Ru interconnect to enlarge the process window and enable multi-layers of high-aspect ratio", will be presented by Giulio Marti, R&D engineer, as an invited speaker, from 10h15 AM to 10h40 AM.
- “Via resistance optimization at advanced sub-2nm nodes”, will be presented by Assawer Soussou (Lam Research Corporation) et al. (co-authored by imec), from 10h40 AM to 11 AM.
“Addressing integration challenges in direct backside contact of CFET”, will be presented by Cassie Sheng, R&D engineer at imec, from 11h40 AM to 12 PM. These results were created (in part) in the context of the NanoIC project.
Session 3: 3D Packaging & Hybrid Bonding I
- "Evaluation of warpage tolerance of 100 µm dies to achieve void-free bond and 100% assembly yield", will be presented by Abhaysinha Patil, R&D Engineer - Wafer Assembly & Packaging at imec, from 1h55 PM to 2h15 PM.
- “Optimizing direct die-to-wafer hybrid bonding: the role of scanner precorrection in achieving fine overlay performance”, will be presented by Imene Jadli, R&D engineer at imec, from 2h45 PM to 3h05 PM.
Session 4: Materials and Unit Process I
- "Ion beam deposition of ruthenium for interconnect applications in a direct metal etch approach", will be presented by Rutvik J Mehta (Veeco Instruments Inc), co-authored by imec, from 3h50 PM to 4h10 PM.
"UV surface pre-treatment and wet cleaning of Ruthenium MP18 semi-damascene structures", will be presented by Fulya Ulu Okudur, R&D engineer at imec, from 4h10 PM to 4h30 PM.
These results were created (in part) in the context of the NanoIC project.
Wednesday, June 4th
Session 6: Advanced Interconnects II
- "MP16/18 integration in Ru semi-damascene using SiN-based core for spacer-is-dielectric SADP", will be presented by Gilles Delie, R&D engineer at imec, from 9h45 AM to 10h05 AM.
- "Electrical test demonstration for 0.55 NA EUV single patterning damascene process", will be presented by Stéphane Larivière (imec/TMC), from 10h25 AM to 10h45 AM.
Session 7: Reliability and Characterization
- "Quantifying the impact of thermal gradients on electromigration lifetimes in 90 nm CD Cu Lines", will be presented by Youqi Ding (KUL/imec), from 11h30 AM to 11h50 AM.
- "AI-driven variability-aware physics-based EM simulation framework for Jmax estimation", will be presented by Ahmed Saleh (KUL/imec), from 11h50 AM to 12h10 PM.
Session 8: Materials and Unit Process II
- "The intermixing study of Cu/Ru interface in dual-damascene scheme for advanced interconnect", will be presented by Sunyoung Noh (Samsung Electronics Co., Ltd.), co-authored by imec, from 3 PM to 3h20 PM.
Session 9: Advanced Interconnects III
- "Integration of through-dielectric-via on buried power rail and slit nano through-silicon-via for enhanced backside connectivity", will be presented by Peng Zhao, R&D engineer at imec, from 4h20 PM to 4h40 PM.
- "Two-metal-level semi-damascene interconnect with variable width bottom metal at metal pitch 18-26 nm and aspect ratio 4-6 routed using fully self-aligned via", will be presented by Anshul Gupta, Principal Member of Technical Staff at imec, from 5 PM to 5h20 PM.
Thursday, June 5th
Christopher J Wilson, Equipment and Material Supplier Portfolio Director at imec, will chair all presentations in Session 11 – Advanced Interconnects IV, from 9h20 AM to 10h30 AM.
Session 11: Advanced Interconnects IV
- "Optimized two metal level semi-damascene interconnects for superconducting digital logic", will be presented by Blake Hodges, Superconducting Design Engineer at imec, as an invited speaker, from 9h45 AM to 10h10 AM.
Session 12: BEOL Integration and Characterization
- "Robust overlay control in 2-level semi-damascene", will be presented by Yannick Hermans, R&D Engineer at imec, from 11h40 AM to 12 PM.
- "Thermally-induced morphology changes in subtractive Ru lines and their mitigation", will be presented by Houman Zahedmanesh, Principal Member of Technical Staff at imec, from 12 PM to 12h20 PM.
About
The 28th edition of the International Interconnect Technology Conference (IITC) will be held at the Westin JOSUN Busan hotel in Busan, Korea on June 2-5, 2025. This is the first IEEE IITC 2025 held in Korea. Authors are encouraged to submit their original work describing Innovative research and development in the critically important field of on-chip interconnects. The conference seeks papers on all aspects of BEOL/MOL interconnects and metallization, including design, unit process, integration and reliability. IEEE IITC 2025 is sponsored by the IEEE Electron Devices Society as the premier conference for interconnect technology devoted to leading-edge research in the field of advanced metallization and 3D integration for ULSI IC applications.
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