Imec will be participating in 18th IEEE International Memory Workshop 2026, a conference that brings the memory community together in a workshop environment to discuss the memory process and design technologies, applications, market needs and strategies. Join us to learn more on our latest breakthroughs and how to work with imec:
PRESENTATION(S)
- TUTORIAL
- Cross-technology co-optimization for Memory density and bandwidth (Invited)
Tutorial 1: Memory Enabled Systems
Dwaipayan Biswas, Program Director XTCO Memory
- SESSIONS
- [2.1] Special Talk: 50 yr History of IMW (Invited)
Session #2 - NAND I
Jan Van Houdt, Fellow - [4.3] Balancing Memory Window and Write Speed in MFSM Capacitors for Non-Destructive Read-Out FeRAM
Session #4 8:30AM – 10:10AM Advanced and Emerging Memories I
Taras Ravsher, R&D Engineer - [5.3] Advancements in Gate Length Scaling and Process Optimization for 3D DRAM Selector Transistors
Session #5 - DRAM II
Eren Canga, R&D Engineer - [6.3] 3D Charge Coupled Device for High-Density and Cost-Efficient Buffer Memory
Session #6 - Memory Enabled Systems
Rishabh Kishore, R&D Engineer - [6.5] Design Architecture Trade-offs for Hybrid Bonded Array-Periphery VBL 3D-DRAM
Session #6 - Memory Enabled Systems
Hyungrock Oh, Researcher - [7.3] Investigation of Erase Mechanism in Gate Side Injection Devices and its Optimization With an Oxide Semiconductor Channel
Session #7 - NAND II
Laurent Breuil, Researcher - [8.3] Analysis and Mitigation for Row Hammer in IGZO based eDRAM at Advanced FinFET Node
Session #8 - Advanced and Emerging Memories II
Arvind Sharma, R&D Engineer - [P9S] Quantitative Analysis of On-Current Discrepancy Between Monocrystalline Si and IGZO Channels in Stacked 3D-DRAM Transistors
Poster Session
Jiseok Hong - [P23] Systematic Failure Mode Analysis and Yield Enhancement of STT MRAM Arrays via Interconnect Patterning and Process Optimization
Poster Session
Debashish Basu, Scientific Director
COMMITTEE
- Organizing committee (Finance Chair):
- Ludovic Goux, Department Director
- Advisory committee:
- Antonio Arreghini, R&D Manager