/IEEE Symposium on VLSI technology & circuits

IEEE Symposium on VLSI technology & circuits

16 - 20 June 2024 | Honolulu, Hawaii

Bridging the digital & physical worlds with efficiency & intelligence

Imec will be present at the 2024 IEEE Symposium on VLSI Technology and Circuits with 18 contributions, including 14 first-authored papers, one co-authored paper, a workshop, a short course and a panel session.

 

Imec highlights

  • Monolithic Complementary Field Effect Transistors (CFET) demonstrated using Middle Dielectric Isolation and Stacked Contacts, Steven Demuynck et al.
  • Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs using Rare-Earth Oxide-based Dipole-First Gate Stack Compatible with CFET Integration, Hiroaki Arimura et al.
  • Extremely scaled perpendicular SOT-MRAM array integration on 300mm wafer, Farrukh Qayyum Yasin et al.
  • Toward 0 V ESD protection in 2.5D/3D advanced bonding technology, Shih-Hsiang Lin et al.
  • Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5), Subrat Mishra et al.
  • EOT scaling via 300mm MX2 dry transfer - Steps toward a manufacturable process development and device integration, Souvik Ghosh et al 
  • A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS, Jorge Lagos et al.
  • C24.5 A 10GS/s Hierarchical Time-Interleaved ADC for RF-sampling applications, Nereo Markulic et al.

Overview imec contributions

Workshops, short courses and panels

Technology Workshop 2: Novel Metals and Advanced Interconnects
Organizers: Christoph Adelmann, Zsolt Tőkei, imec

  • Workshop on “Novel Metals for Advanced Interconnects” by Christoph Adelmann, imec and other speakers from Intel, ASM International, Rensselaer Polytechnic Institute, Tohoku University, Destination 2D and University of California Santa Barbara and University of Texas at Arlington

Technology Short Course : Advanced VLSI technologies for next generation computing

  • “Functional Backside: past, present, and STCO future” by James Myers, imec

Panel session: Will AI Bite the Industry That Feeds It?

  • With Serge Biesemans, imec and other panelists from Qualcomm, KLA, SKHynix, Stanford University, Nvidia and KAIST.

 

Papers

Session T3: Novel Channel Materials for Advanced CMOS

  • EOT scaling via 300mm MX2 dry transfer - Steps toward a manufacturable process development and device integration, Souvik Ghosh et al
  • Single-crystalline monolayer MoS2 arrays based high-performance transistors via selective-area CVD growth directly on silicon wafers, Guixu Zhu et al (co-authored by imec)

Session T5: Advanced CMOS Devices and Technology-1

  • Monolithic Complementary Field Effect Transistors (CFET) demonstrated using Middle Dielectric Isolation and Stacked Contacts, Steven Demuynck et al.
  • Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5), Subrat Mishra et al.
  • Backside Power Delivery in High-Density and High Performance Context: IR-drop and Block-level Power-Performance-Area Benefits, Yun Zhou

Session T9: Monolithic and Heterogeneous Integration

  • Mitigating line-break defectivity with a sandwiched TiN or W layer for metal pitch 18 nm aspect ratio 6 semi-damascene interconnects, Anshul Gupta et al.
  • Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias, Peng Zhao et al.
  • Toward 0 V ESD protection in 2.5D/3D advanced bonding technology, Shih-Hsiang Lin et al.

Session C18: Data Converter Techniques

  • A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS, Jorge Lagos et al.

Session T10: Emerging Non-Volatile Memories - RRAM, FeRAM, PCM, MRAM-2

  • Extremely scaled perpendicular SOT-MRAM array integration on 300mm wafer, Farrukh Qayyum Yasin et al.

Session T11: Advanced CMOS Devices and Technology-2

  • Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs using Rare-Earth Oxide-based Dipole-First Gate Stack Compatible with CFET Integration, Hiroaki Arimura et al.

Session C23: Neural Recording Interfaces

  • A Highly-Integrated 1536-Channel Quad-Shank Monolithic Neural Probe in 55nm CMOS for Full- Band Raw-Signal Recording, Xiaolin Yang et al.
  • A 16-Ch CMI-Tolerant Neural AFE with Inherent CM Detection and Shared CM Suppression Achieving 0.006mm2/Ch and 3.1μW/Ch, Joan Aymerich et al.

Session C24: High-Speed Data Converters

  • C24.5 A 10GS/s Hierarchical Time-Interleaved ADC for RF-sampling applications, Nereo Markulic et al.

Session T17: Memory Technology: NAND, DRAM-2

  • DRAM-peri FinFET – A Thermally-stable High-Performance Advanced CMOS RMG Platform with Mo-based pWFM for sub-10nm DRAM, Jishnu Ganguly et al.

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