Imec at IEEE IEDM 2022

Imec will be present at the 2022 IEEE International Electron Devices Meeting (IEDM) as (co-)author of no less than 21 papers, including 3 invited papers and two IEDM committee highlighted papers. Imec’s contributions show progress in logic, memory, interconnect, 3D integration and quantum computing technologies. The invited papers discuss devices for advanced RF and colloidal quantum dot for image sensor technologies. Serge Biesemans, senior vice president semiconductor R&D at imec, will take part in the panel “75 years of transistor technology – (no) time for retirement?”. Imec will also host two short courses: “Process Architectures Changes to Improve Power Delivery” by Geert Hellings, program director DTCO at imec, and “Innovative 3D Technologies for Memory-Compute Integration” by Geert Van der Plas, scientific director & program manager 3D system integration at imec. Ben Kaczer, scientific director, will give a tutorial on “FEOL reliability: from essentials to advanced and emerging devices and circuits”.

Imec highlights

6.4 High performance La-doped HZO based ferroelectric capacitors by interfacial engineering, M. Popovici et al.

Capacitors based on trilayer stacks of TiO2/La-doped hafnium zirconate/Nb2O5 show record high remnant polarization 2Pr of 66.5 µC/cm2 after 3x106 cycles at 3 MV/cm or an endurance of up to 1011 cycles with a final 2PR of ~30 µC/cm2 at 1.8 MV/cm depending on the Hf and Zr precursors used.

11.5 III-V/III-N technologies for next generation high-capacity wireless communication (Invited), N. Collaert et al.

In this paper, we will discuss the progress that has been made in upscaling GaN and InP to a Si platform as well as making them CMOS and 3D compatible to enable the heterogeneous systems that will be needed for 5G mm-wave and 6G sub-THz frequencies for high-capacity wireless communication.

15.3 Thermal Modelling of GaN & InP RF Devices with Intrinsic Account for Nanoscale Transport Effects (Invited), B. Vermeersch et al.

We present a Monte Carlo thermal modelling framework with partial experimental validation suited for simulating complex 3D device geometries. Steady state and transient case studies on GaN HEMTs and InP nanoridge HBTs reveal peak temperature rises that are up to threefold larger than conventional predictions based on bulk diffusion.

19.3 Colloidal quantum dot image sensors: a new vision for infrared (Invited), P. Malinowski et al.

Short-wave infrared (SWIR) range carries information vital for augmented vision. Colloidal quantum dots (CQD) enable monolithic integration with small pixel pitch, large resolution and tunable cut-off wavelength, accompanied by radical cost reduction. In this paper, we describe the challenges to realize manufacturable CQD image sensors enabling new use cases.

23.2 Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells, V. Vega-Gonzalez et al.

An innovative semi-damascene integration scheme enabling the new 4-track standard-cell routing architecture called VHV relevant for the beyond-2nm node is demonstrated. The required boundary between cells is built with two vias with zero-line extension facing each other and an aggressive T2T=8.9nm in between, all self-aligned to the top 18nm-pitch layer.

36.2 First demonstration of field-free perpendicular SOT-MRAM for ultrafast and high-density embedded memories, K. Cai et al.

For the first time, we experimentally demonstrate the field-free switching in multi-pillar (MP) spin-orbit torque magnetic random-access memory (SOT-MRAM) devices, which are CMOS-compatible 300mm integrated perpendicular MTJs (p-MTJs). This FFS scheme is fully compatible with the standard integration process and the voltage-gated SOT (VG-SOT) switching in MP devices.

Panel discussion

Tuesday, Dec 6, 2022, 8-10pm

75 years of transistor technology – (no) time for retirement?

Organizers: Stefan De Gendt, imec and Suman Datta, Georgia Institute of Technology

In celebration of the 75th anniversary of the first working transistor, made by Walter Brattain and John Bardeen, IEDM  will host an entertaining and insightful evening panel discussion on the importance and future of this vanishingly small and yet irreplaceable miracle technology for the next 75 years.

With imec experts Stefan De Gendt, fellow at imec and Serge Biesemans, senior vice president semiconductor R&D at imec

Courses and tutorials

Saturday, December 3, 2022

Tutorial

FEOL reliability: from essentials to advanced and emerging devices and circuits by Ben Kaczer, scientific director 

When designing any new VLSI technology, a wide range of complex, mutually interdepend considerations related to the materials, processing, and electrical performance need to be optimized. Moreover, sufficient performance must be guaranteed for the entire expected lifetime of the end product. This essential reliability requirement unfortunately disqualifies many highly performing material combinations and device designs, thus making reliability a critical component of technology progress. In this tutorial we will argue that dependable long-term reliability projections based on accelerated tests can be made only if the true physical nature of the degradation is well understood. After a brief introduction to probability and statistics, we will discuss the main degradation mechanisms occurring in present-day and future Field-Effect Transistors (FETs), such as Nanosheets and Forksheets. These mechanisms include SILC (Stress Induced Leakage Current), TDDB (Time-Dependent Dielectric Breakdown), BTI (Bias Temperature Instability), RTN (Random Telegraph Noise), and HCD (Hot Carrier Degradation) with the accompanying Self-Heating (SHE) and will be linked with the underlying properties of defects. We will show that these defects play the essential role in many emerging technologies and applications, including CryoCMOS and 2D FETs, and are responsible for degradation variability in deeply scaled devices. Finally, we will discuss how device degradation can be accounted for in circuit simulations and show how in-depth knowledge of defect properties can be used to our advantage to design new devices and applications.

Sunday, December 4, 2022

Short Course 1: High-Performance Technologies for Datacenter and Graphics to enable Zetta Scale Computing

SC1-5: Process Architectures Changes To Improve Power Delivery by Geert Hellings, program director DTCO

Backside power delivery offers a solution for a challenge that has plagued VLSI technology since long. A traditional BEOL has to distribute a variety of signals across the chip: short range connections forming the fabric of logic cells, long busses moving data back and forth between the cores and the memories, clock signals and also power delivery. This has lead to a lot of compromises since each of these functions comes with different requirements (low Resistance, low Capacitance, low cross-talk, predictable insertion delay, …). Hence moving the power connections to the backside of the wafer allows to individually optimize the BEOL for signal distribution while optimizing the backside metals for efficient power delivery. This is of course a promising perspective. However it requires a great deal of process innovation e.g. wafer bonding, extreme wafer thinning, backside-to-frontside patterning alignment. Backside power delivery is such a profound modification that it enters at every abstraction level in a DTCO flow (Design Technology Co-Optimization). This short course will give an overview of the different process architectures that are being considered for backside power delivery: from Powervia, Buried Power Rail to direct backside contact and compare their properties in terms of process complexity, device performance impact and consequences at standard cell library and block level.

Short Course 2: Next-Generation High-Speed Memory for AI and High Performance Compute

SC2-6: 3D System integration for memory compute applications by Geert Van der Plas, scientific director & program manager 3D system integration

To cope with ever more data processing needs, 3D integration has emerged as a prime technology to extend Moore’s law. In this presentation we will introduce system architecture concepts that improve memory compute capability: chiplets and 3D system on chip (3D-SOC). The chiplet approach enables larger amounts of compute to be combined with dense, high bandwidth memory. Currently chiplets are integrated side by side. Ultimately, they will be stacked in 3D. The 3D-SOC concept re-uses the system on chip approach, extending it to the third dimension. Compute and memory are co-designed, removing overhead of chip-to-chip interfaces to improve performance, power, area and cost. We will review the 3D technology roadmaps supporting the implementation of these system architectures. Silicon interposer and bridges integrated into advanced packages are key to realize the chiplet based systems. Fine pitch RDL first or last approaches offer alternatives to the Silicon based interconnect. Scaled die to wafer solder micro-bump and direct bonding interconnects increase interconnect density, increasing bandwidth. Wafer-to-wafer hybrid bonding offersthe highest interconnect density, reaching sub-micron pitches that enable fine grain partitioned 3D-SOC systems. We discuss recent progress and remaining challenges in technology development and design enablement. We explain how 3D system integration will be a key pillar of data-centric computation in the next era.

Paper overview

Monday, December 5, 2022

Session 5: Reliability of Memory Technologies and Systems

• 5.1 Understanding the Cycling-Dependent Threshold Voltage Instability in OTS Devices, M. Yamaguchi*, R. Degraeve (imec) et al. (*KULeuven)

Session 6: MT - Ferroelectric Memory

• 6.4 High performance La-doped HZO based ferroelectric capacitors by interfacial engineering, M. Popovici et al.

Session 8: MS - Advancing Moore's Law

• 8.6 OTS Physics-based Screening for Environment-friendly Selector Materials, D. Matsubayashi*, S. Clima et al. (*KULeuven)

Tuesday, December 6, 2022

Session 11: MAT - Advanced Devices for High RF and THz Applications

• 11.5 III-V/III-N technologies for next generation high-capacity wireless communication (Invited), N. Collaert et al.

Session 13: MS - Ferroelectrics: From Modeling of Wake-up and Endurance to Novel Circuits

• 13.1 Multi-domain Phase-field Modeling of Polycrystalline Hafnia-based (Anti-)ferroelectrics Capable of Representing Defects, Wake-up and Fatigue, S-C Chang*, K. Chae*, M. Popovici et al. (*Intel)

Session 15: MS - Advanced TCAD Methodology

• 15.3 Thermal Modelling of GaN & InP RF Devices with Intrinsic Account for Nanoscale Transport Effects (Invited), B. Vermeersch et al.

Session 17: RSD/MS – Focus Session - DNA Digital Data Storage, Transistor Based DNA Sequencing, and Bio-Computing

• 17.4 The Nanopore-FET as a High-Throughput Barcode Molecule Reader for Single-Molecule Omics and Read-out of DNA Digital Data Storage (Invited), K. Martens et al.

Session 19: ODI - Photonic Technologies and Non-Visible Imaging

• 19.3 Colloidal quantum dot image sensors: a new vision for infrared (Invited), P. Malinowski et al.

Session 23: ALT - Design-Technology CoOptimization and System Technology CoOptimization

• 23.1 Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures, H. Mertens et al.
• 23.2 Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells, V. Vega-Gonzalez et al.
• 23.3 Insights into Scaled Logic Devices Connected from Both Wafer Sides, A. Veloso et al.
• 23.4 Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network, R. Chen et al
• 23.5 Cryo-Computing for Infrastructure Applications: A Technology-to-Microarchitecture Cooptimization Study, Divya Prasad*, Manoj Vangala*, Mudit Bhargava*, Arnout Beckers et al. (*Arm Inc)

Wednesday, December 7, 2022

Session 26: MT - Charge-Based Memories

• 26.2 FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits, E. Capogreco et al.

Session 30: RSD - Reliability of Transistor Technology

• 30.1 Characterizing and Modelling of the BTI Reliability in IGZO-TFT using Light-assisted I-V Spectroscopy, Z. Wu et al.
• 30.4 Low thermal budget PBTI and NBTI reliability solutions for multi-Vth CMOS RMG stacks based on atomic oxygen and hydrogen treatments, J. Franco et al.
• 30.5 New insights on the excess 1/f noise at cryogenic temperatures in 28 nm CMOS and Ge MOSFETs for quantum computing applications, R. Asanovski*, A. Grill et al. (*Universit`a degli Studi di Modena e Reggio Emilia)
• 30.6 Back Barrier Trapping Induced Resistance Dispersion in GaN HEMT: Mechanism, Modeling, and Solutions, Hao Yu et al.
• 30.7 Comprehensive Investigations of HBM ESD Robustness for GaN-on-Si RF HEMTs, S. Abhinay et al.

Session 34: ALT - Advanced CMOS: Technology and Devices

• 34.1 Low temperature source / drain epitaxy and functional silicides: essentials for ultimate contact scaling, C. Porret et al.

Session 36: EDT - Magnetic and Ferroelectric Technologies

• 36.2 First demonstration of field-free perpendicular SOT-MRAM for ultrafast and high-density embedded memories, K. Cai et al.