/Smaller, Better, Faster: imec Presents Chip Scaling Roadmap

Smaller, Better, Faster: imec Presents Chip Scaling Roadmap

November 9, 2023 | Webinar

The need for increased computing continues growing at an ultra-fast speed, with chip data remarkably still keeping in line with Moore’s law. This momentum is expected to carry on even as 2D scaling becomes increasingly challenging via introduction of new device architectures and materials, scaling boosters such as Backside-Power-Delivery-Network (BSPDN), overall Design-Technology-Co-Optimization (DTCO)-driven design improvements, 3D chip stacking and the introduction and adoption of System-Technology-Co-Optimization (STCO).

Logic standard cell scaling remains at the core of the roadmap, with continued advances in holistic patterning using EUV/high-NA EUV lithography key for enabling cost-effective scaling and lower energy consumption as it allows a reduced number of process steps/complexity. At transistor level, the move from finFETs to vertically stacked nanosheet (NS) FETs is predicted to help continue delivering profitable node-to-node scaling gains, beyond which 3D stacked CMOS, also called CFET, where NMOS and PMOS are folded on top of each other by a monolithic or 3D sequential approach appear as the ultimate scaling limit of the NSFET family of devices. In parallel, to take full advantage of multiple innovations at transistor level, de-coupling signal and power wiring by using both wafer sides for routing, thus enabling BSPDN, is a new concept that has been gaining traction with various types of device connectivity options possible and under exploration. It also shows the expansion potential towards other functions (namely by addition of specific devices after wafer’s backside processing), paving the way to a truly functional backside. The latter has high value proposition given that System-on-Chips (SOCs) are in fact vastly heterogeneous systems. From computing blocks to memorization, CMOS devices/circuits perform here a wide variety of functions, including the whole infrastructure that wraps the system (power and clock distribution, short and long signal nets, IOs and PLLs,…). As such, to continue obtaining enhanced system performance increasingly requires embracing this heterogeneity. That can be done by leveraging the unique capabilities of logic, memory and 3D technologies under the umbrella of STCO, while reviewing system design practices and introducing novel architectures and devices.

Scaling is thus entering a new era, aiming higher flexibility and more options for system optimization, progressively moving from CMOS towards a future CMOS heterogeneous platform: CMOS 2.0.


  • Anabela Veloso - Principal Member of Technical Staff, imec
  • Pete Singer - Editor-in-Chief, Semiconductor Digest