2022 IEEE Symposium on VLSI Technology & Circuits
13 - 17 June 2022 | Honolulu, Hawaii, USA | Hybrid
This year at the 2022 IEEE Symposium on VLSI Technology & Circuits, imec has 20 contributions: 16 papers (of which one invited), one course on embedded memory scaling, one workshop about recent advances in radar, mm-wave, and sub-THz, and a speaker at the Circuit Panel on building the 2030 workforce. The papers cover a wide range of topics such as logic and memory technologies and applications, advanced interconnect, wireless technologies, and biomedical systems. Michael Peeters, Vice President R&D for Connectivity, will present an invited paper on wireless heterogeneous integration. Additionally, Jan Rabaey, CTO System Technology Co-Optimization (STCO), is one of the panelists of the Circuit Panel “Building the 2030 Workforce: How to attract great students and what to teach them?”.
Imec highlights
(Why do we need) Wireless Heterogeneous Integration (anyway?) (invited)
By Michael Peeters
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails - (conference highlight paper)
Anabela Veloso et al.
FinFETs with a novel routing scheme enabling connection via buried power rails (BPR) from both wafer sides. On frontside, contacting to S/D & BPR is done in one metallization step with optimized preclean reducing Rext & preserving BPR-VBPR interface. On backside, scaled nTSVs land on BPR. P/NMOS show improved ION-IOFF, BTI behavior.
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node
Rongmei Chen et al.
In this paper, backside power delivery network (BS-PDN) and a high density 2.5D Mimcap (Metal-insulator-metal capacitor) are applied to improve dynamic IR- drop of 2D and 3D ICs at sub-2nm node. Benefits of BSPDN+2.5D Mimcap as double boost for improving the IR drop of 2D and 3D ICs are demonstrated.
A 128-Channel AC-Coupled 1st-order Δ-Δ∑ IC for Neural Signal Acquisition
Xiaolin Yang et al.
This paper presents a 128-channel NRIC for the simultaneous acquisition of LFPs and APs. The proposed architecture achieves rail-to-rail EDO rejection, low power and small area, while providing low noise and large input range. The chip has been fully validated in saline, demonstrating its capability to record full-band neural signals.
First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP
Gayle Murdoch et al.
In this paper we demonstrate the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects from 26 to 18nm metal pitch (MP), fabricated on 300mm wafers. We have developed a novel integration flow, using the principle of subtractive etching of Ru, on 2 subsequent metal levels. Using structures with programmed overlay shift, we demonstrate the functionality of a fully self-aligned via process which results in working devices with placement errors of up to 5nm. Furthermore, we show via-to-line breakdown field > 9MV/cm, confirming FSAV.
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
Anne Vandooren et al.
3D sequential stacking is demonstrated using top tier planar devices on bottom tier bulk finfet devices. 3D top-bottom layer interconnectivity is validated through functional 3D via chains and CMOS inverters. Three different Si layer transfer flows, including a low temperature Smart CutTM, are compared electrically for top tier planar devices.
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
Pieter Schuddinck et al.
We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.
Courses, workshops, and panels
Monday 13 June - Technology Short Course: Monolithic and Heterogeneous Integration
Embedded Memory Scaling with Monolithic 3D Integration
Gouri Sankar Kar
This short course aims to provide a general overview of different embedded memory solutions and their challenges and will also provide future suggestions.
Tuesday 14 June - Circuit Panel
Building the 2030 Workforce: How to attract great students and what to teach them?
Jan Rabaey
Jan Rabaey, CTO System Technology Co-Optimization (STCO) at imec, is one of the panelists of this Circuit Panel, alongside other experts from Yonsei, MIT, Intel, Meta and MediaTek.
Tuesday 14 June - Technology Panel
What will it take to bring new material from Lab to Manufacturing?
Naoto Horiguchi
Naoto Horiguchi, Director CMOS device technology at imec, is one of the panelists of this Technology Panel, alongside other experts from ASM, Air Liquide, Kioxia, Univ of Tokyo and SRC.
Thursday 16 June - Circuit Workshop 1
Recent Advances in Radar, Mm-Wave, and Sub-THz: Technology, Circuits, and Packaging
Organized by Nereo Markulic (imec) and Gernot Hueber (Silicon Austria Labs)
This workshop is focused on millimeter-wave radars advancing the role of wireless systems in social infrastructure. We highlight some recently developed systems in a versatile radar application space. Renowned presenters from, both, industry, and academia discuss key technological aspects, circuit design and packaging needed for successful industrialization of modern MMW radar systems
Papers
Tuesday 14 June
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
Anabela Veloso et al.
Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt >0 V and Ion >30 µA/µm
Subhali Subhechha et al.
Wednesday 15 June
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node
Rongmei Chen et al.
First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP
Gayle Murdoch et al.
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
Anne Vandooren et al.
Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode
Taras Ravsher et al.
High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories
Romain Ritzenthaler et al.
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO
Kateryna Serbulova et al.
Insight to Data Retention loss in ferroelectric Hf0.5Zr0.5O2 pFET and nFET from simultaneous PV and IV measurements
Md Nur Kutubul Alam et al.
Wafer Level Pixelation of Colloidal Quantum Dot Image Sensors
Yunlong Li et al.
Scalable 1.4 µW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements
Rohith Acharya et al.
A 128-Channel AC-Coupled 1st-order Δ-Δ∑ IC for Neural Signal Acquisition
Xiaolin Yang et al.
Thursday 16 June
(Why do we need) Wireless Heterogeneous Integration (anyway?) (invited)
Michael Peeters
Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories
Kaiming Cai et al.
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
Pieter Schuddinck et al.
Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters
Bjorn Vermeersch et al.