SDSi: a new generation of workload-adaptable chips through reconfigurable computing

The exploding demands of AI processing—both in data centers and at the edge—are intensifying the need for domain‑specific chips. Yet the rising cost and complexity of designing custom silicon make such solutions impractical for many applications that lack the required scale.

This tension has renewed interest in a concept originating in the 1960s: reconfigurable computing, which allows hardware architectures to be adapted to specific workloads after manufacturing.

What is reconfigurable computing?

Reconfigurable computing is a computer architecture that combines two approaches to computation:

• Fixed-function computation, typically performed by application-specific circuits (ASICs) that offer high speed but low flexibility, as the circuit cannot be changed after manufacturing.
• Programmable computation, typically executed on general‑purpose processors (CPUs) or accelerators (GPUs), offering high flexibility but lower performance and energy efficiency compared to dedicated hardware.

Reconfigurable computing brings together the efficiency of the former and the flexibility of the latter, enabling hardware architectures that can adapt to changing workloads.

Granularity is an important parameter for reconfigurable hardware, referring to the smallest functional unit that can be independently reconfigured, with important implications for flexibility, performance, and overhead.

The best-known example of reconfigurable hardware is the field‑programmable gate array (FPGA). An FPGA can be configured at the bit level after manufacturing. FPGAs are well suited for highly parallel workloads and applications that involve extensive bit‑level manipulation, such as signal processing and certain accelerator functions.

FPGAs offer significantly more architectural flexibility than application‑specific circuits. However, this comes at a cost: compared to custom hardware, FPGAs incur substantial area, energy, and performance overheads.

Software-defined silicon (SDSi): reducing reconfiguration overhead

Software-defined silicon (SDSi) is a compute system paradigm where the hardware architecture of the system can be configured by the software executing on the compute system.

An SDSi chip is made as a blank canvas consisting of a variety of reconfigurable blocks, optimized for specific functions (arithmetic, memory, etc.). Before running any application, these blocks are configured to best suit different parts of the application or application domain.

Because of the coarser granularity of the reconfigurable fabric compared to FPGAs, the reconfiguration overhead is reduced, allowing for more efficient run-time reconfiguration.

Benefits of SDSi

Software-defined silicon aims to:

• Lower the chip cost by enabling larger sales volumes, reducing the non-recurring engineering (NRE) cost per chip.
• Increase energy efficiency and performance because the architecture can be configured to better suit the application.

As a reconfigurable platform, SDSi not only reduces the cost but also allows it to be carried by three entities:

• the provider of the canvas
• the provider of the architecture
• the providers of the software