Tokyo Electron to Collaborate with imec-ASML Joint High NA EUV Research Laboratory

Tokyo Electron (TEL; Head Office: Minato-ku, Tokyo; President: Toshiki Kawai) announced today the company will introduce its leading-edge Coater/Developer to the imec-ASML joint high NA EUV research laboratory (joint high NA lab) in Veldhoven, the Netherlands. The equipment will be integrated inline* with EXE:5000, ASML’s next-generation high NA EUV lithography system with a 0.55 numerical aperture (NA), scheduled to be operational in 2023. By collaborating with imec and ASML, TEL will continue to pursue technological development to meet the ongoing scaling needs of its customers.

High NA EUV lithography is expected to provide more advanced pattern scaling solutions compared to conventional EUV lithography. The Coater/Developer being introduced to the joint high NA lab will feature advanced capabilities which are not only compatible with widely used chemically amplified resists and underlayers, but are also compatible with spin-on metal-containing resists. Spin-on metal-containing resists have demonstrated high resolution and high etch resistance, and are expected to enable finer patterning. However, metal-containing resists also require sophisticated pattern size control as well as metal contamination control on the backside and bevel of the wafer. To meet these challenges, the Coater/Developer being installed at the joint high NA lab comes with leading-edge process modules capable of handling metal-containing resists.

Combined with the new process modules, a single unit of TEL Coater/Developer can process a wide variety of materials inline, including chemically amplified resists, metal-containing resists, and underlayers. This will enable flexible fab operation, while also realizing increased productivity and high availability that are among the advantages of a Coater/Developer.

Taking advantage of the breadth of its products spanning several adjacent processes, TEL is forming a partnership with resist materials suppliers to provide comprehensive patterning solutions covering etch processes as well as Coater/Developer for lithography processes.

Yoshinobu Mitano, TEL Corporate Director, Senior Vice President and General Manager of SPE Business Division, said, “TEL is honored to collaborate with imec and ASML at the joint high NA lab to further understand and solve the challenges of high EUV NA patterning. By leveraging our experience in high volume manufacturing of EUV lithography process technology, we intend to deliver high NA EUV process solutions to our customers’ fabs in a timely manner.”

Keiichi Akiyama, Vice President and CTSPS BU General Manager of TEL, commented, “As the manufacturer currently holding 100% of market share in inline Coater/Developer for EUV lithography, we look forward to working with the joint high NA lab to realize the most advanced Coater/Developer for next-generation high NA EUV lithography. In collaboration with our partners, we will introduce and validate cutting-edge approaches and technologies to address our customers’ challenges.”

Rudi Cartuyvels, Chief Operating Officer and Executive Vice President R&D of imec, stated, “For more than 25 years imec and TEL have been strategic partners in developing innovative solutions to advance semiconductor scaling. imec is looking forward to continuing this collaboration with TEL to enable the next step on the semiconductor scaling roadmap, high NA patterning.”

Steven Scheer, Vice President Advanced Patterning, Process and Materials at imec, said, “The collaboration between TEL and imec has been key in identifying and eliminating critical defects in EUV patterning with spin-on resist, contributing to the introduction of EUV in high volume manufacturing. For high NA EUV patterning, with thinner resist films and at smaller feature sizes, defect reduction will be even more important. Therefore, imec is pleased to be working with TEL and resist material suppliers in the Joint imec-ASML High NA Lab to enable an accelerated introduction of high NA EUV in the industry.”

* Inline: The state of being a part of a continuous process line. In this instance, it refers to the integration of a lithography system and a Coater/Developer, which means a smaller footprint and higher productivity for customers.