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Luc Van den hove

Vision

Why our chip strategy will determine our future 

Rohith Acharya

Anton Potočnik

Asser Elsayed

Ruoyu Li

Kristiaan De Greve

Cryo-CMOS electronics interfacing with superconducting qubits; a fab-compatible process targeting key elements for Si spin qubit upscaling

Research update

Both Si spin qubit and superconducting qubit based platforms are viable candidates for quantum technology upscaling, which drives the migration of research efforts from lab- to fab-based environments.

Common challenges include compatibility with large-scale industrial manufacturing techniques and electronics development for reading and controlling the growing number of qubits.

Imec reports progress for each platform: cryo-electronics for interfacing with superconducting qubits and a 300mm CMOS platform targeting Si spin qubit upscaling key elements.

Progress in upscaling Si spin and superconducting based quantum technologies

Jade Liu

Imec’s new SiGe BiCMOS optical receiver allows to process ever-increasing amounts of datacenter traffic

200 gigabits per second 

Bart Placklé

- How a tiny building block could help reshape an entire ecosystem -

Is the Automotive Industry Ready to Confront Its Greatest Challenge Yet?

Liesbet Lagae

“You can make things happen by working just a little bit harder, day by day.”

Testimonial

<ul>
	<li>Obtained a PhD in nanoelectronics (spintronics, MRAM, spin transfer torque) in 2003</li>
	<li>Started at imec as team leader spintronics in that same year</li>
	<li>Pivoted the team to create the first life sciences technology group at imec as an R&amp;D manager LST in 2006</li>
	<li>Appointed program director life sciences in 2016</li>
	<li>Occupies the position of associate professor at KU Leuven’s biophysics department since 2008</li>
	<li>Became an imec fellow in 2020</li>
</ul>

Meet imec fellow Liesbet Lagae

Melina Lofrano

Xinyue Chang

Herman Oprins

Zsolt Tokei

A modeling framework to accurately predict heat dissipation in the chip’s back-end-of-line

Longread

As dimensional scaling continues, the heating of the interconnects in the chip’s <a href="/en/expertise/cmos-advanced/compute/beol">back-end-of-line (BEOL)</a> has become a growing concern, as it can compromise the chip’s reliability.

Imec presents a modeling framework that accurately predicts heat dissipation in advanced BEOL structures, considering the coupling with the logic cells in the front-end-of-line (FEOL) and boundary conditions from packaging technologies.

This article discusses the model and its added value. Valuable insights are presented, such as the dominant contribution of low-k dielectrics and via layers to the BEOL’s thermal resistance.

Mitigating the thermal bottleneck in advanced interconnects 

Imec’s Zsolt Tökei discusses the latest outcome of imec's research on binary and ternary alloys for advanced interconnect metallization schemes with Silicon Semiconductor’s Phil Alsop.

Featured in the media

Resistivity research uncovers thin film star material

How imec is driving autonomous innovation

Jo De Boeck

Imec’s Jo De Boeck talks about the ITF World highlights in EE Journal’s Fish Fry podcast

Super Human Perception and New Compute Paradigms: How imec is Driving Autonomous Innovation

New drug measurement and monitoring technology for accurate assessment of drug concentrations in blood, paves the way for personalized and faster care

Axithra, a spin-off of imec and Ghent University, raises 10M Euro

<a class="btn" href="/en/introduction-integrated-circuits">Follow our online course</a>

Looking for an introduction to microchips?

Julien Ryckaert

Imec highlights the potential of backside power delivery for high-performance computing and evaluates options for backside connectivity

Some major chip manufacturers recently announced the introduction of a backside power delivery network (BSPDN) in their logic roadmap.

In this article, imec, in collaboration with Arm, presents a design-technology co-optimization (DTCO) of one specific implementation of a BSPDN, where nTSVs and buried power rails are used for backside routing. They show how the potential of this BSPDN scheme can be fully harvested in a high-performance compute context.

In addition, they introduce alternative options for backside connectivity at the standard cell level, observing the largest scaling potential for a direct backside connectivity scheme.

Backside power delivery options: a DTCO study

Imec integrates thin-film pinned photodiode into SWIR sensors

Results published in Nature Electronics unlock the potential of thin-film sensors in infrared imaging

Imec integrates thin-film pinned photodiode into superior short-wave-infrared imaging sensors

Tom Aernouts

Molecular interface engineering: a pathway to scalable manufacturing

Metal halide perovskites show great promise for next-generation photovoltaic cells. However, commercialization requires industry-compatible processing techniques to address stability issues.

The largest efficiency losses and instability of perovskite solar cells are reported at the interfaces between the perovskite absorber and charge transport layers.

In this article, dr. Tom Aernouts presents an ammonium salt treatment to enhance two critical interfaces, creating highly efficient, stable, and scalable perovskite cells.

Stories

Why our chip strategy will determine our future

Progress in upscaling Si spin and superconducting based quantum technologies

200 gigabits per second

Meet imec fellow Liesbet Lagae

Mitigating the thermal bottleneck in advanced interconnects

Resistivity research uncovers thin film star material

How imec is driving autonomous innovation

Axithra, a spin-off of imec and Ghent University, raises 10M Euro

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