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Shane (Shih-Hsiang) Lin

Marko Simicic

Nicolas Pantano

Guidelines for protecting the internal I/O interfaces from electrostatic discharge during die or wafer bonding steps

Longread

The continuous scaling of interconnect densities in 2.5D/3D technologies leaves little room for implementing ESD protection circuits at the internal I/O interfaces.

This forces industry to invest more heavily in ESD prevention during die-to-die and die-to-wafer bonding steps, and to avoid over-design of the ESD protection circuits.

Doing that in the most efficient way requires a more fundamental understanding of the ESD events that happen at the internal I/O interfaces.

This article presents useful insights, translated into practical guidelines and research directions for circuit designers and bonding tool suppliers.

Towards efficient ESD protection strategies for advanced 3D systems-on-chip 

Imec achieves record-low charge noise for Si MOS quantum dots fabricated on a 300mm CMOS platform 

Jade Liu

The results highlight the maturity of 300mm fab-based qubit processes ultimately enabling large-scale quantum computers&nbsp;

Nicolas Le Thomas

Ultraviolet (UV) improves resolution and specificity in optical applications but is still difficult and costly to implement

Photonic integrated circuits (PICs) -combining all key optical functions into a single chip- are poised to revolutionize UV microscopy, but also applications in other areas, such as pharmacology or quantum computing

Imec-UGhent developed the first UV-PICs with low propagation losses

They demonstrate an enhanced resolution and field of view for super-resolution microscopy applications

How ultraviolet photonic integrated circuits transform microscopy

Eric Beyne

Geert Van der Plas

Bridging the gap: innovations in chiplet interconnect technology

Chiplets are small chips with a well-defined function that can be incorporated with other chiplets into a single package or system.

Dense interconnections between chiplets ensure fast, high-bandwidth electrical connections. This article discusses both interposer and 3D integration approaches that aim to scale pitches below 1µm.

Chiplets: Piecing Together the Next Generation of Chips (Part I)

Steven Scheer

Opening of the joint ASML-imec High NA EUV Lithography Lab: milestone in preparing High NA EUV for adoption in mass manufacturing

Vision

On the eve of the High NA EUV Lithography era, Steven Scheer, senior vice president of compute technologies &amp; systems / compute system scaling at imec, talks about the significance of the joint ASML-imec High NA EUV Lithography Lab for the semiconductor industry.

He highlights the applications that will benefit from transitioning to High NA EUV, and how this transition will impact CO2 emissions.

Looking forward, he explains how imec and its partners will further push the High NA EUV patterning ecosystem into the next generations.

Entering the High NA EUV Lithography era

Julien Ryckaert

A new approach to miniaturization with greater versatility for compute system optimization

Julien Ryckaert, VP Logic Technologies at imec, explains how CMOS 2.0 brings heterogeneity inside the compute system-on-chip (SoC), as such addressing a broader variety of compute specificities.

He identifies advanced 3D interconnect and backside technologies as instrumental to realize this concept...

... and calls upon the semiconductor ecosystem to adapt to this new way of approaching miniaturization.

CMOS 2.0: bringing heterogeneity inside the system-on-chip

Inside imec's N2 P-PDK workshop

Anita Farokhnejad

Sara Louahdi

Hands-on training grants academia and industry access to cutting-edge semiconductor technologies.

Blog

Imec’s N2 P-PDK workshop explores advanced semiconductor design strategies.

Participants from industry and academia gain hands-on N2 design experience, using tools from Synopsis and Cadence.

Imec’s initiative supports global semiconductor innovation and is closely tied to the European Chips Act objectives.

Unlocking tomorrow's technology nodes: inside imec's N2 P-PDK workshop

Leap in Belgian quantum communication infrastructure: first QKD links  

New leap in Belgian quantum communication infrastructure: imec, UGent and Belnet realize first QKD links  

Carolina Mora Lopez

New research into higher-density neural probes, more extensive electrode coverage of the brain surface, and electrical stimulation ability.

Research update

This article highlights recent advancements in neurotechnology, presented in three papers at the 2024 VLSI Circuits Symposium.

A new high-density readout IC for multiplexed channels allows for large-scale recordings of brain-surface activity.

Imec’s latest neural probe for deep-brain recordings features a record-high channel count and improved performance compared to the state of the art.

A novel technique to suppress stimulation artifacts in brain recordings holds promise for combined stimulation/recording implants.

Advancing neurotech from brain surface to brain depths 

Imec introduces best-in-class ADCs for base stations and smartphones

Imec introduces best-in-class ADCs for base stations and smartphones, propelling beyond-5G communications

Imec demonstrates functional monolithic CFET devices with stacked bottom and top contacts

Joris Van Campenhout

"At imec, you find yourself in a unique situation. Make true use of it."

Testimonial

<ul>
	<li>Joined imec in 2010</li>
	<li>Photonics engineer, program manager optical I/O, chief technologist silicon photonics, program director optical I/O</li>
	<li>Became imec fellow in 2020&nbsp;</li>
</ul>

Meet imec fellow Joris Van Campenhout

Imec unveils CMOS-based 56Gb/s zero-IF D-band beamforming transmitter

Designed to support next-generation, short-range, high-speed wireless services at frequencies above 100GHz – from wireless fail-safes in data centers to extended reality (XR) solutions

Stories

Towards efficient ESD protection strategies for advanced 3D systems-on-chip

Imec achieves record-low charge noise for Si MOS quantum dots fabricated on a 300mm CMOS platform

How ultraviolet photonic integrated circuits transform microscopy

Chiplets: Piecing Together the Next Generation of Chips (Part I)

Entering the High NA EUV Lithography era

CMOS 2.0: bringing heterogeneity inside the system-on-chip

Inside imec's N2 P-PDK workshop

Leap in Belgian quantum communication infrastructure: first QKD links

Advancing neurotech from brain surface to brain depths

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