Design of next-generation Wi-Fi on Software-Defined Radio

Digital communication plays a pivotal role in professional environments, supporting persons, machines as well as things to interact with each other over a communication network. In professional environments, such as industry automation (industry 4.0/5.0), communication becomes increasingly diverse, more reliable, time-critical, and subject to change over time. For purposes such as mobility, flexibility, or cost, wireless connectivity – in various forms, from sensor networks to high-capacity networks - has become an integral part of professional networking environments.

Extrapolating these trends of how professional applications will evolve over the next 10 years, we want to advance wireless communications to the next level on these aspects: end-to-end latency, time synchronization accuracy among distributed applications across diverse network segments, reliability/QoS for high-priority and safety-critical traffic.

Today, we are far from achieving that vision, as most research is limited to theoretical or simulation studies due to a lack of validation opportunities in real systems. Such studies ignore real-world impairments which are hindering uptake of wireless innovations in real-world application scenarios. Some examples of impairments are non-ideal RF hardware, complex and dynamic wireless channels, limited digital processing capabilities in terms of clock speed and footprint, quantization errors due to conversion from floating to fixed point, etc. 

To bridge the gap from theory and simulation to experimentation, we are seeking a passionate researcher who is ready to take the leap. Two options, software-defined radio or commercial radio chips, both have their limitations. Software-defined radio with PHY functionality implemented in software and controlled by a host PC, does not allow real-time operation needed to support real-world low latency use cases that require fast response times. Commercial radio chips are blackboxes with closed firmware and drivers and restrict innovation and experimentation to the higher-layer networking functionality above firmware and driver with limited real-time interaction. Therefore, significant research efforts are required to open up and advance chip design by tackling many challenges: 

• Deep understanding of future Wi-Fi standards, especially the PHY and Low MAC for the new features such as (coordinated) OFDMA, or (distributed) MU-MIMO.
• Highly efficient hardware design of advanced features in upcoming Wi-Fi standards beyond Wi-Fi 6/7 optimizing performance and footprint for deployment on FPGAs.
• Synchronization technology to support coordinated multi-AP operation coming in the near future.
• Software-hardware co-design achieving true real-time operation for time-critical applications serving a massive number of users/machines with diverse/guaranteed QoS, targeting end-to-end KPIs (between end-to-end applications).
• Small-scale end-to-end proof-of-concept validation in the field.
• Cost and energy-efficient solutions allowing large-scale deployment.

This Ph.D. vacancy targets to address these challenges, delivering solutions of the advanced Wi-Fi chip for professional end-to-end communication networks that stand out in fulfilling, guaranteeing the challenging requirements of ultra-reliable and time-and-safety-critical applications running on top.