/Digitally assisted calibration of RF sampling ADCs

Digitally assisted calibration of RF sampling ADCs

Leuven | More than two weeks ago

Towards co-optimization of digitally assisted calibration and circuit design

In the dynamic landscape of wireless communication, where speed and reliability are paramount, one of the crucial components are high-speed Analog-to-Digital Converters (ADCs). Future wireless communication standards demand ultra-high data rates which in turn require ADCs operating at high sampling rates (>10 GS/s), high effective accuracy (> 8 bits), and high linearity. ADC designers face the challenging task of striking an optimal balance between power consumption, high bandwidths, and linearity requirements, among other factors. As CMOS technologies continue to scale down, the pursuit of a highly linear ADC grows increasingly challenging. This is because high linearity and elevated power consumption generally go hand in hand. Broadly, there are two ways to tackle this linearity challenge. The most widely recognized approach includes creative circuit-level and system-level design for pioneering novel ADC systems and architectures. An alternative approach relies on digital calibration to mitigate the non-ideal behaviour of the ADC. Throughout this PhD research, the focus will be on investigating and developing digital (non)linear calibration techniques to enhance ADC performance. This PhD will serve as a stepping stone towards achieving co-optimization between digitally assisted calibration and circuit design.


The objective of this PhD research is to pioneer calibration techniques tailored for contemporary high-speed ADCs. These envisioned correction algorithms must be executed directly on the chip, which imposes unique constraints which make the research interesting and challenging. The initial phase of the PhD program will involve the proposition of candidate models capable of rectifying the non-ideal characteristics of the ADC. You will start by performing circuit and system-level simulations using models of the state-of-the-art ADCs developed at IMEC. The proposed models should also lend themselves to efficient implementation in Digital Signal Processing (DSP) systems and system identification algorithms for the proposed models will be formulated and put into practice. The combination of the chosen model and the identification algorithm will provide the specifications required for establishing a measurement setup wherein all elements converge. The lessons and constraints leaned during this PhD will contribute directly to the co-development of the next generation high-speed ADCs. You will collaborate with a team of expert designers which are eager to implement these algorithms to improve the performance of their next designs.


This PhD aims to combine the expertise of IMEC and the Vrije Universiteit Brussel (VUB). At IMEC, you will join the team of Jan Craninckx and Piet Wambacq, one of the world-leading groups in high-performance RF, millimeter-wave and ADC design, with a strong publication record in the major conferences and journals of the solid-state circuits community. At the VUB, you will be embedded within the ELEC department, renowned for its expertise in nonlinear system identification and signal processing.

Required background: Signal processing, circuit modelling and simulation, RF measurements

Type of work: 10% literature, 20% circuit-level simulation, 60% programming, 20% measurements

Supervisor: Piet Wambacq

Co-supervisor: Dries Peumans

Daily advisor: Adam Cooman, Nereo Markulic

The reference code for this position is 2024-080. Mention this reference code on your application form.

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