Explainable Neurosymbolic Algorithms for Process Optimization in Semiconductor Manufacturing

General research domain:
Artificial Intelligence

Description:

Semiconductor manufacturing processes could benefit from the integration of Artificial Intelligence (AI) solutions to perform process monitoring and control, such as yield forecasting and detecting process inefficiencies or defects towards performing process optimizations. These AI solutions aim to learn typical process behaviours under various conditions based on historical data. However, such classical AI systems are unable to take advantage of the rich, tacit domain expertise of experienced semiconductor process engineers pertaining to these behaviours. Neurosymbolic AI aims to resolve this by enabling the representation of this domain expertise as Knowledge Graphs and fusing it into the machine learning pipelines. As such, the AI can learn from both the historical data as well as the domain knowledge to perform optimal process monitoring and steering [1]. However, current hybrid AI solutions have found limited adoption due to (a) the tedious process of transforming the tacit process knowledge into Knowledge Graphs, (b) the limited availability of neurosymbolic methods that perform accurate fusion of sequential knowledge (e.g. a process consisting of different steps) into machine learning methods, and (c) the lack of explainability of the neurosymbolic predictions, leading to lack of trust in the outcomes. To overcome these challenges, this PhD aims to explore the design of user-friendly, explainable and process-aware neurosymbolic methods to accelerate and enhance the integration of AI in semiconductor manufacturing processes. The research will establish a foundational framework for applying neurosymbolic AI in this domain, emphasizing three core pillars: knowledge-driven modelling, explainability, and result reliability:

1.      Ontology-Based Knowledge Representation

The first pillar focuses on lowering the barrier towards capturing tacit domain knowledge on process flows, parameters and their interdependencies in a Knowledge Graph. The goal is to bypass the need for extensive interactions and synchronization between domain experts and knowledge engineers by employing Large Language Models (LLMs). Through automated extraction it needs to be investigated how LLMs can form a baseline ontological representation of the available process knowledge (manuals, flow charts, reports, etc.), which can then be subsequently enhanced through limited feedback loops between the LLM and domain expert. The end result is an ontology that captures the hierarchical and relational structure of semiconductor manufacturing processes, enabling a shared and machine-interpretable knowledge base.

 

2.      Design of explainable techniques for embedding process knowledge into machine learning

The second pillar focuses on developing methods to integrate knowledge graphs into machine learning methods, in such a manner that the temporal and sequential nature of the process knowledge and properties are maintained. This includes designing mechanisms to leverage structured domain knowledge during training and inference, as well as discovering new relationships from data to enrich the knowledge graph. To ensure the trustworthiness of the resulting neurosymbolic method, this embedding process should be transparent, allowing to attribute back the predictions towards the features in the Knowledge Graph that mostly steered it. Most existing embedding methods are uninterpretable, as they assume latent feature spaces, therefore the focus within this research will be on enhancing more transparent embedding techniques, such as binary features and walk-based techniques.

3.      Application Layer: Trustworthy Predictive and Optimization Tasks

The third pillar applies the designed algorithms and framework to real-world semiconductor manufacturing scenarios. This stage will demonstrate how the combined Knowledge Graph and Neurosymbolic approach can address predictive tasks, such as yield forecasting, defect detection, and process optimization, ensuring both accuracy and explainability. Additionally, this stage will explore how LLMs can act as an interface between the neurosymbolic predictions, the Knowledge Graph and the end users to accurately contextualize and translate the outputs to the process engineers.

[1] Yuwei Wan, et al. “Making knowledge graphs work for smart manufacturing: Research topics, applications and prospects”, Journal of Manufacturing Systems, Volume 76, 2024, Pages 103-132, https://doi.org/10.1016/j.jmsy.2024.07.009.

Expected Contributions:

• Reusable Semiconductor Ontology and Knowledge Graph Generation Pipeline: A formal ontology for semiconductor processes, along with a knowledge graph (KG) construction pipeline based on LLMs, competency questions, and validation artifacts to ensure semantic consistency and interoperability
• Explainable and Process-aware neurosymbolic framework: Novel methods for embedding temporal and sequential process knowledge into machine learning algorithms, delivering models that are explainable and trustworthy
• LLM-Enhanced Knowledge Mediation: Exploration of large language models (LLMs) as a bridge between symbolic and neural layers—enabling interpretation of prediction outputs back into the KG and generating candidate rules or constraints to enrich the knowledge base.
• Demonstrations on Semiconductor Tasks: Application of the proposed framework to critical use cases such as virtual metrology, yield risk prediction, defect detection, and tool drift monitoring, showcasing measurable improvements in accuracy, interpretability, and robustness.