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I/O Cells ESD Design and IBIS Modeling
Master internship - Leuven | Just now
Every chip talks to the world through its I/O, and this project is about making sure that conversation is fast, accurate, and survives the unexpected.
| This internship project addresses two practical challenges in I/O circuit design and reliability at advanced CMOS technology nodes. |
| The first task is to establish a validated IBIS modeling flow for high-speed I/O standards, starting with LVDS. This involves running SPICE-level simulations of transmitter and receiver behavior, generating IBIS models through existing toolflows, and verifying their accuracy by correlating SPICE and IBIS simulation results. A reusable testbench and clear documentation will be produced so that the flow can be applied to future I/O standards with minimal rework. |
| The second task targets ESD robustness of a bidirectional I/O cell in GF 22 nm technology, where a known ESD failure has been identified. The intern will reproduce the failure in simulation, identify the root cause in terms of device stress and ESD requirements, and propose and verify circuit-level solutions that reduce voltage overstress on 1.8 V devices during ESD events. |
| Both tasks are expected to produce working simulation flows, verified results, and reusable documentation that can support ongoing and future I/O design and reliability work within the team. |
Type of internship: Master internship
Duration: 6 months
Required educational background: Electrotechnics/Electrical Engineering
Supervising scientist(s): For further information or for application, please contact Evgenii Timokhin (Evgenii.Timokhin@imec.be) and Henrique Caldas Kessler (Henrique.CaldasKessler@imec.be) and Viktor Tupikin (Viktor.Tupikin@imec.be) and Giancarlo Franciscatto (Giancarlo.Franciscatto@imec.be)
The reference code for this position is 2026-INT-180. Mention this reference code in your application.
Imec allowance will be provided.
Applications should include the following information:
- resume
- motivation
- current study
Incomplete applications will not be considered.